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Visitor assaad1-
Visitor
328 Views
Registered: ‎10-16-2018

ERROR in vhdl

I get the following error message:

ERROR:HDLParsers:3566 - xst/work/hdpdeps.ref line 20 Invalid date/time (".vhd") found.

When I press on ERROR I get to the Xilinx site and it can't find explanation . Also i get in all directory file (xilinx) :hdllib.ref and hdpdeps.ref in XST . how i can fix this error ?

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6 Replies
Moderator
Moderator
317 Views
Registered: ‎03-16-2017

Re: ERROR in vhdl

Hi @assaad1-,

 

Check if this thread helps you out, https://forums.xilinx.com/t5/Archived-ISE-issues-Archived/WebPAck-compilation-error/td-p/4051

 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Visitor assaad1-
Visitor
285 Views
Registered: ‎10-16-2018

Re: ERROR in vhdl

thanks sir for you reply, i did that and its work but when i did again its happen the same errors shows 

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Moderator
Moderator
272 Views
Registered: ‎03-16-2017

Re: ERROR in vhdl

Hi @assaad1-,

 

Create this project from scratch and check if the issue persists or not. 

 

If it does not help, then provide your testcase to evaluate it at our end. Which ISE version are you using?

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Visitor assaad1-
Visitor
257 Views
Registered: ‎10-16-2018

Re: ERROR in vhdl

i create the  project from scratch and stil the same error and "im using fixed package"

 im using  ISE 9.2i  version 

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Moderator
Moderator
248 Views
Registered: ‎03-16-2017

Re: ERROR in vhdl

Hi @assaad1-,

Please provide the archive project to evaluate it at our end. 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Visitor assaad1-
Visitor
237 Views
Registered: ‎10-16-2018

Re: ERROR in vhdl

I apologize, I have not stated that there is also this warning that I have not understood and also when I do the synthesis I find in the xst folder(work folder) that there are two files: hdllib.ref and hdpdeps.ref and after I delete it makes the correct synthesis and just after I redo the synthesis the errors come back.

 

warning :WARNING:HDLParsers:3623 - An error occured while attempting to sort the source files in the project file C:/Xilinx92i/LST_vhdl/LST_module_vhdl.prj. Processing will continue with the source files in the order given. You may wish to disable sorting.

also the same error :ERROR:HDLParsers:3566 - xst/work/hdpdeps.ref line 13 Invalid date/time (".vhd") found.

thankyou sir for your times 

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