UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer multiprobe
Observer
7,770 Views
Registered: ‎06-26-2014

Elaboration/Synthesis drops ports from block design

Hi,

 

I am using  Vivado 2014.4, I seem to have an issue with one of my block designs.

 

I have a few output ports in my block design, which get ignored after elaboration step.

 

I also get warnings : "[Common 17-55] 'set_property' expects at least one object. ["C:/Users/sowmya/Desktop/backups/PS_Top_21May/PS_Top.srcs/constrs_1/new/PS_plus_fabric_wrapper.xdc":33]"

 

For each of the constraint line where i try to set an IOSTANDARD or a PACKAGE_PIN property yo these ports.

 

Why are the ports being dropped? I tried deleting and recrating these ports, no change.

 

Attaching screenshots of relevant constraints,block design, and the warnings

constraints_prvoided_and_critical_warning.png
problem_ports_circled_in_Red.png
0 Kudos
2 Replies
Scholar pratham
Scholar
7,762 Views
Registered: ‎06-05-2013

Re: Elaboration/Synthesis drops ports from block design

@multiprobe go to tcl console and run 

 

Get_ports

This tcl command returns all the ports,

You should be able to see these ports. If output of this tcl command does not include led_right,left and so then these ports are not there and you should check for synthesis warnings,this may give a clue what is happening with these ports

-Pratham

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
Moderator
Moderator
7,750 Views
Registered: ‎01-16-2013

Re: Elaboration/Synthesis drops ports from block design

Hi,

 

You can also use the following command in "open synthesized design" 

show_objects -name find_1 [get_ports -filter { NAME =~ "*" } ]

 

This command will list all the IO ports of your design where you can set the properly set the IOSTANDARD and Site using the drop down menu as shown below. When you save the design then the changes will get reflected in XDC file.

 

 

get_ports.PNG

 

If you do not see the LED ports with above command then as suggested by Pratham check synthesis the log file or warnings on these ports.

 

--Syed

 

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
---------------------------------------------------------------------------------------------

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
0 Kudos