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Visitor leofr
Visitor
5,277 Views
Registered: ‎05-19-2011

Error on design with 3-state data bus synthesis

Hi. Can you help to solve the problem?

I created an embedded processor (Microblaze for Spartan 6), using EDK/SDK (ISE 12.3), instantiated it into Project Navigator and connected it to schematic/VHDL logic. In microblaze processor I use EMC (external memory controller) with 3-state data bus (Mem_DQ). Syntax check and behavioral simulation are OK, but synthesis tool (XST) gives errors:

 

Multi-source in Unit <Tropa_EDK> on signal <D_CPU<0>>; this signal is connected to multiple drivers.

…………………………………………………………..…………………………………………………………..

Multi-source in Unit <Tropa_EDK> on signal <D_CPU<15>>; this signal is connected to multiple drivers.

 

(Tropa_EDK – name of Progect Navigator project; D_CPU – 3-state bus, connected to Mem_DQ.

 

As I saw in *.vhd file, generated for behavioral simulation of Microblaze processor, IOBUF Xilinx primitive is used by EDK for 3-state data bus. But synthesis tool (XST) doesn’t “understand” this primitive and doesn’t allow 3-state data bus to have several drivers.

I can’t synthesize my Project Navigator design because of errors during synthesis. Can you help to solve this problem?

P.S. I use declaration of UNISIM library and attribute "user_black_box" while instantiation of Microblaze processor.

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4 Replies
Scholar drjohnsmith
Scholar
5,267 Views
Registered: ‎07-09-2009

Re: Error on design with 3-state data bus synthesis

hi

 

tri state buss's are not an internal signal to the FPGA,

   they can only be connectred to IO pins of the FPGA.

 

are you trying to connect the tri state pins of a block thats designed to drive the out side,

   like the memory side of the EMC ?

 

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Visitor leofr
Visitor
5,260 Views
Registered: ‎05-19-2011

Re: Error on design with 3-state data bus synthesis

Thanks a lot.

Could you prompt, what is the usual way of data exchange between Microblaze and registers of VHDL/schematic logic?

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Scholar drjohnsmith
Scholar
5,257 Views
Registered: ‎07-09-2009

Re: Error on design with 3-state data bus synthesis

Hi

 

I think you need at this point to talk to a tutor / mentor a bit , these are fundamental questions, 

    the answers will affect your projet.

 

 

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Historian
Historian
5,249 Views
Registered: ‎02-25-2008

Re: Error on design with 3-state data bus synthesis

 


@leofr wrote:

Thanks a lot.

Could you prompt, what is the usual way of data exchange between Microblaze and registers of VHDL/schematic logic?


 

Wrong forum, but ... and as Dr John mentions, this question is Processors 101 basic stutf ...

 

You do realize that the MicroBlaze talks to the PLB, and the PLB's data bus is actually two buses, one for input (to the MicroBlaze) and the other is an output (from the MicroBlaze)?

 

When you write to a register, you load it with the data presented on the write data bus (qualified by the address, write enable, etc). On the read side, all registers, and anything else that the processor might wish to read (memory, I/O ports) are all inputs to a super-big mux which is selected by the address.

 

The only time one really sees bidirectional I/O buses is at a processor's pins, which are usually at a premium on the package. Internally? Never. No need for them.

----------------------------Yes, I do this for a living.
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