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6,746 Views
Registered: ‎08-16-2014

Errors during synthesis

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Hello, I am new to Vivado. I tried to synthesize the Basic_IPI_Design_Zedboard_2013p2 on Vivado 2014, but it doesn't work. There is an error that says:

[Synth 8-3493] module 'design_1' declared at 'E:/Zedboard/Basic_IPI_Design_ZedBoard_2013p2/Basic_IPI_Design_ZedBoard_2013p2/Basic_IPI_Design/Basic_IPI_Design.srcs/sources_1/bd/design_1/hdl/design_1.vhd:1658' does not have matching formal port for component port 'btns_5bits_tri_o' ["E:/Zedboard/Basic_IPI_Design_ZedBoard_2013p2/Basic_IPI_Design_ZedBoard_2013p2/Basic_IPI_Design/Basic_IPI_Design.srcs/sources_1/imports/hdl/design_1_wrapper.vhd":121]

There are 3 some other similar errors. There (unfortunately for me) must be some difference between Vivado 2013 and 2014 that breaks this reference design. The download is at http://zedboard.org/sites/default/files/design/Basic_IPI_Design_ZedBoard_2013p2.zip

 

I am new to Vivado and not sure how to troubleshoot this kind of problem. Is there a guidebook or something that explains the concepts behind the Vivado process? If I understood more of what was going on, then I might be able to troubleshoot it myself.

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vemulad
Xilinx Employee
Xilinx Employee
11,044 Views
Registered: ‎09-20-2012

Hi,

 

Can you regenerate the block design wrapper file and see if it helps (right click on .bd file and select "create wrapper")?

 

If you have upgraded the IP's in Vivado 2014.x then there could be chance that the IP ports might have changed which is the reason for the error. As the other poster suggested make sure that the component declaration matches the module instantiation.

 

If you still see the issue then attach the design here. The link you specified is not accesible.

 

Thanks,

Deepika.

Thanks,
Deepika.
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3 Replies
yenigal
Xilinx Employee
Xilinx Employee
6,739 Views
Registered: ‎02-06-2013

Hi

 

Looks like you have port mismatch's in the component file and the top level files using this component which has changed between version.

 

Check the files mentioned in the error messages and make sure that the component file and the top level file have the same ports instantiated and used.

Regards,

Satish

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vemulad
Xilinx Employee
Xilinx Employee
11,045 Views
Registered: ‎09-20-2012

Hi,

 

Can you regenerate the block design wrapper file and see if it helps (right click on .bd file and select "create wrapper")?

 

If you have upgraded the IP's in Vivado 2014.x then there could be chance that the IP ports might have changed which is the reason for the error. As the other poster suggested make sure that the component declaration matches the module instantiation.

 

If you still see the issue then attach the design here. The link you specified is not accesible.

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

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6,689 Views
Registered: ‎08-16-2014
Both answers were correct.

From sources view I could open design_1_wrapper.vhd and design_1 and see that there is a port mismatch between them. I regenerated the wrapper by removing the old one from project + delete contents on disk, then created a new HDL wrapper by clicking the block design in the sources view.
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