02-04-2019 07:51 PM
I am using Kintex-7 FPGA (xc7k325tffg900-2). In my design I have a block diagram with many blocks. I also have additional logic which is not in block diagram but implemented in Verilog code. For our application we want to gate clocks going to some blocks in the block diagram. So I have added an AND gate using 'Utility Vector Logic' in block diagram to gate the clock. But after adding this AND gate and compiling the design I am getting a large number of errors from Vivado during the implementation phase. I am attaching a screenshot showing these error messages. Before adding clock gating this design was compiling without errors and I was able to generate a .bit file. But now I am getting these errors.
Can you please help with this situation?
Thank you so much!
02-06-2019 11:18 PM
You need to take special care to implement clock gating. You can do that by using a BUFGCE or BUFHCE and drive the CE-Pin synchronously to the clock that should go through the buffer.
Alternatively, you can `gate' your IP by utilizing the CE-Pin of the Flipflops, but that has to be designed into the IP properly.
You really shouldn't use a LUT to drive a clock.
Also, you have a lot of clocks in your design. Take care that there are only 16 BUFGs in each of the top/bottom halves of the 7 series devices. You might be running out of them. Try placing a few of those clocks on BUFHs if possible.
02-07-2019 07:57 PM
Thank you so much for your feedback. I am using BUFGCE now. I was able to create an IP with it and include it in the block diagram. After updating the block diagram I am trying to synthesize and implement the design. But during the synthesis stage I am getting several errors indicating that some modules are not found. I am looking at those errors and trying to upgrade those IPs. So far I have not been able to complely synthesize the design. This was a working design and the only change I made was to add an IP in the block diagram which would gate the clock using BUFGCE. So the errors seen during synthesis don't make much sense to me.
Thank you so much.
02-07-2019 08:02 PM
What error message are you seeing in synthesis?
02-07-2019 10:21 PM
Thank you so much for your response. I am attaching screenshots showing the following items.
1) Error messages
2) Source code where this block is still present
3) Block diagram where this block is still present and connected.
This design was working and generating a bit stream without errors. But after adding BUFGCE using IP block it is generating these error messages during synthesis.
Please help with this situation.
Thank you so much.