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aditya04
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Registered: ‎06-12-2021

F7 F8 MUX in Synthesis

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How can I force vivado to pick F7 and F8 Muxes instead of LUTs. Also for the synthesis of 16x1 Multiplexer, it is inferring 2 F7 Muxes and 1 F8 mux, how can I force it to pick 3 F7 muxes instead.

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maps-mpls
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Registered: ‎06-20-2017

>Is there any circuit or design other than 8x1 Multiplexer or 16x1 Multiplexer (or further multiplexer) that uses F7 and/or F8 Mux during synthesis in vivado? 

 

Yes.  As @avrumw said, they can be used by the tools to create boolean functions of 7 or 8 variables (indeed, in some cases, F7MUxes can be used for boolean equations of 13 variables, e.g., 6 inputs to one LUT6, 6 other inputs to another LUT6 in the same slice, combined with another input and the output of the two LUT6s.  For example, in a clocked process, the following code

if(some_bit = '1') then
  y <= aa XOR bb XOR cc XOR dd XOR ee xor ff;
else
  y <= Il XOR mm XOR nn XOR oo XOR pp xor qq;
end if;

 could end up in a single slice using two LUT6s one for aa through ff, the other for ll through qq, an F7MUX with some_bit and the output of the two LUTs, and a register. 

However, be aware that the tools to meet other requirements may not use the F7MUX.  For example, if there is an advantage for placement/routing congestion/timing in using two LUT6s followed by another LUT6, the tools will do this.

In general, you should let the synthesizer be the synthesizer.  The number of times you actually need to force the use of an F7MUX is pretty small.  As in, I haven't ever had to do it other than as an academic exercise.  You'd be better off learning HDL, slice architecture, interconnect architecture, and timing analysis in my view.  Forcing certain primitives in your design prematurely can lead to all sorts of headaches (and possibly job security--but not the good kind of job security, though).

*** Destination: Rapid design and development cycles *** Unappreciated answers get deleted, unappreciative OPs get put on ignored list ***

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drjohnsmith
Teacher
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Registered: ‎07-09-2009

this has been a feature of xilxin tools for well over  a decade,

   they just dont want to use the F7 

https://www.xilinx.com/support/documentation/application_notes/xapp522-mux-design-techniques.pdf

https://www.xilinx.com/support/documentation/white_papers/wp274.pdf

http://ebook.pldworld.com/_semiconductors/Xilinx/DataSource%20CD-ROM/Rev.6%20(Q1-2002)/userguides/V2_handbook/ug002_ch2_multiplexers.pdf

 

 

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aditya04
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Registered: ‎06-12-2021

Is there any circuit or design other than 8x1 Multiplexer or 16x1 Multiplexer (or further multiplexer) that uses F7 and/or F8 Mux during synthesis in vivado? 

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drjohnsmith
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Registered: ‎07-09-2009

Im certain @aditya04 ,there are circuits that use mux's as well as real muxs;

   Hay  in the old days, we used to use any old gate spare on a board if it saved a new package,

       a 4  to one Mux made a great 2 input gate for any function,

 

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avrumw
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Registered: ‎01-23-2009

Also for the synthesis of 16x1 Multiplexer, it is inferring 2 F7 Muxes and 1 F8 mux, how can I force it to pick 3 F7 muxes instead.

This is architecturally impossible.

The only inputs to the F7 MUX are the outputs of the LUTs immediately adjacent to them. The only inputs to the F8 MUX are the F7 MUXes in the same slice.

These are the sole purpose of these MUXes

  • F7 MUX: to combine the output of two 6-input LUTs to create a 7 input function (hence the name F7 MUX)
  • F8 MUX: to combine the output of two F7 MUXes (each of which is a 7 input function) to create an 8 input function (hence the name F8 MUX)

Avrum

maps-mpls
Mentor
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355 Views
Registered: ‎06-20-2017

>Is there any circuit or design other than 8x1 Multiplexer or 16x1 Multiplexer (or further multiplexer) that uses F7 and/or F8 Mux during synthesis in vivado? 

 

Yes.  As @avrumw said, they can be used by the tools to create boolean functions of 7 or 8 variables (indeed, in some cases, F7MUxes can be used for boolean equations of 13 variables, e.g., 6 inputs to one LUT6, 6 other inputs to another LUT6 in the same slice, combined with another input and the output of the two LUT6s.  For example, in a clocked process, the following code

if(some_bit = '1') then
  y <= aa XOR bb XOR cc XOR dd XOR ee xor ff;
else
  y <= Il XOR mm XOR nn XOR oo XOR pp xor qq;
end if;

 could end up in a single slice using two LUT6s one for aa through ff, the other for ll through qq, an F7MUX with some_bit and the output of the two LUTs, and a register. 

However, be aware that the tools to meet other requirements may not use the F7MUX.  For example, if there is an advantage for placement/routing congestion/timing in using two LUT6s followed by another LUT6, the tools will do this.

In general, you should let the synthesizer be the synthesizer.  The number of times you actually need to force the use of an F7MUX is pretty small.  As in, I haven't ever had to do it other than as an academic exercise.  You'd be better off learning HDL, slice architecture, interconnect architecture, and timing analysis in my view.  Forcing certain primitives in your design prematurely can lead to all sorts of headaches (and possibly job security--but not the good kind of job security, though).

*** Destination: Rapid design and development cycles *** Unappreciated answers get deleted, unappreciative OPs get put on ignored list ***

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