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wwwxxx
Visitor
Visitor
9,804 Views
Registered: ‎11-10-2008

FATAL_ERROR:HDLParsers:vhptype.c:174:$Id: vhptype.c,v 1.9 2005/08/22 17:03:34 mikev Exp $:200 - INTERNAL ERROR

Hi everyone:

 

I just ecounter this error , and don't knwo how to solve it:

 

"FATAL_ERROR:HDLParsers:vhptype.c:174:$Id: vhptype.c,v 1.9 2005/08/22 17:03:34 mikev Exp $:200 - INTERNAL ERROR... while parsing "D:/Documents and Settings/Temp_ME_engine/PE_one.vhd" line 112. Contact your hot line.   Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.

Process "Synthesis" failed"

 

when I just click "View the RTL schematic" for the following code:

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity PE_one is
    Port ( Curr_input : in  STD_LOGIC_VECTOR (7 downto 0);
           Ref_input : in  STD_LOGIC_VECTOR (7 downto 0);
           CSR_mode : in  STD_LOGIC_VECTOR (1 downto 0);
     Cin : in STD_LOGIC;
           EN : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           partial_SAD_input : in  STD_LOGIC_VECTOR (12 downto 0);
           partial_SAD_output : out  STD_LOGIC_VECTOR (12 downto 0);
           Ref_prop : out  STD_LOGIC_VECTOR (7 downto 0);
     Cout : out STD_LOGIC
     );
end PE_one;

architecture STRUCT of PE_one is

signal tmp_Curr : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_AD   : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_AD_1   : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_partial_SAD : STD_LOGIC_VECTOR (12 downto 0);
signal low : STD_LOGIC := '0';
signal tmp_Cout : STD_LOGIC;

--one kbitUnivReg
component kbitUnivReg IS
 GENERIC(DATAWIDTH : INTEGER := 8);
 PORT
 (
  clk           : IN  STD_LOGIC;
  serinl, serinr  : IN  STD_LOGIC;  --left & right shift
  mode            : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);  --
  datain          : IN  STD_LOGIC_VECTOR((DATAWIDTH-1) DOWNTO 0);
  dataout         : out STD_LOGIC_VECTOR((DATAWIDTH-1) DOWNTO 0)
 );
END component;


--one eightbitAD
component eightbitAD is
port (inputA : IN STD_LOGIC_VECTOR (7 downto 0);
  inputB : IN STD_LOGIC_VECTOR (7 downto 0);
  output : OUT STD_LOGIC_VECTOR (12 downto 0)
);
end component;


--one kbitAdder
component kbitAdder is
  generic(DATAWIDTH : natural := 13;         -- top bit
          prop : time := 100 ps);
    port (a    : in  std_logic_vector (DATAWIDTH-1 downto 0);
          b    : in  std_logic_vector (DATAWIDTH-1 downto 0);
          cin  : in  std_logic;
          sum  : out std_logic_vector (DATAWIDTH-1 downto 0);
          cout : out std_logic
    );
end component;


--three latches
component kbitLatch is
generic (DATAWIDTH : INTEGER := 8);
port ( CLK : IN STD_LOGIC;
   D   : IN STD_LOGIC_VECTOR (DATAWIDTH-1 downto 0);
   Q   : OUT STD_LOGIC_VECTOR (DATAWIDTH-1 downto 0)
);
end component;

begin

U0:kbitUnivReg generic map (DATAWIDTH =>8)
     port map(clk => clk, serinl => low, serinr => low, mode => CSR_mode, datain => Curr_input, dataout => tmp_Curr);

U1:eightbitAD port map (inputA => tmp_Curr, inputB => Ref_input, output => tmp_AD);
U2:kbitLatch generic map (DATAWIDTH => 8)
    port map (CLK => clk, D => Ref_input, Q => Ref_prop);
U3:kbitLatch generic map (DATAWIDTH => 13)
    port map (CLK => clk, D => tmp_AD, Q => tmp_AD_1);
U4:kbitLatch generic map (DATAWIDTH => 14)
    port map (CLK => clk, D(13) => tmp_Cout, D(12 downto 0) => tmp_partial_SAD, Q(13) => Cout, Q(12 downto 0) => partial_SAD_output);
U5:kbitAdder generic map (DATAWIDTH => 13)
    port map (a => tmp_AD_1, b => partial_SAD_input, cin => Cin, sum => tmp_partial_SAD, cout => tmp_Cout);
end STRUCT;

 

 

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6 Replies
yinshtony
Visitor
Visitor
9,778 Views
Registered: ‎06-10-2008

I encountered the same problem!!!!!!
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wwwxxx
Visitor
Visitor
9,765 Views
Registered: ‎11-10-2008

problem sloved...

 

I just copy all vhd files to a new folder and create a new project...

 

still don't know why this happened

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yinshtony
Visitor
Visitor
9,759 Views
Registered: ‎06-10-2008

problem sloved!

   Thank you!!!

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shenhuanghui
Visitor
Visitor
9,051 Views
Registered: ‎05-05-2009

I have the same problem when I import the IP PLBv46_Slave to the project via Create & Import Peripheral Wizard.

as you said, copy and create new project. i have tried, but the problem is not resolved yet.

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sabir
Newbie
Newbie
215 Views
Registered: ‎07-25-2021

you can solve the problem with cleaning up the project files. first clean up the project files and then try to synthesize the project.

(project tab/clean up the project files ...)

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varunra
Xilinx Employee
Xilinx Employee
167 Views
Registered: ‎01-24-2017

hi @wwwxxx , 

can your share following information?
1.  complete project, because the code you pasted , vivado will treat the modules as black boxes.

2. which version of vivado are you using

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