What you want to test here? How you will understand the simulation if you haven't coded the RTL?
I am not sure what's your requirement, but you can yourself generate the synthesized netlist using Example designs. Open Xilinx tool (ISE or Vivado) and then open example design. Synthesized it and use it for your testing.
If this doesn't help provide details on what exactly you are trying to do and what help you are looking for.