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Participant
Participant
976 Views
Registered: ‎09-18-2013

FPGA implementation got aborted during FPGA synthesis

Hi,

 

    Got a problem to run vivado version 2016.3. The job was aborted during FPGA synthesis. Using vivado version 2014.4 is fine.

There is no clear message to explain why the job got aborted if running 2016.3.  Could anyone help?

hs_err_pid17532.log and vivado.log.gz files are attached.

 

 

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Moderator
Moderator
925 Views
Registered: ‎07-21-2014

Re: FPGA implementation got aborted during FPGA synthesis

@micrelrogerlo

 

Can you please verify the XDC constraints in your design? Also, check if the wildcard is used properly or not.

Did you check the design in latest Vivado version?

 

Thanks

Anusheel

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Participant
Participant
895 Views
Registered: ‎09-18-2013

Re: FPGA implementation got aborted during FPGA synthesis

Hi Anusheel,

 

      I just wonder why there is no clear message to indicate the reason when the FPGA synthesis job got aborted.

It would be hard to debug. There is quite a lot of constraints. How could we be sure that's the cause?

I tried vivado 2017.3.1  before. I got the same result. The question is why it's okay in 2014.4 but not in the later version?

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Moderator
Moderator
862 Views
Registered: ‎07-21-2014

Re: FPGA implementation got aborted during FPGA synthesis

@micrelrogerlo

 

I agree that such scenarios are hard to debug. Generally, Vivado writes errors and warnings in the log file for all the failures. 

In this case, the tool is crashing while applying the XDC constraints hence I asked to check if there is any visible issue in XDC file.

 

Is it possible for you to share the design? I will share an EZmove link with you to share the files over secured channel.

 

Thanks,

Anusheel

 

 

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Participant
Participant
844 Views
Registered: ‎09-18-2013

Re: FPGA implementation got aborted during FPGA synthesis

Anusheel,

 

     That's would be great. Please let me know what files are needed. Is .dcp file good enough?

 

Roger

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Moderator
Moderator
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Registered: ‎07-21-2014

Re: FPGA implementation got aborted during FPGA synthesis

@micrelrogerlo

 

As the run was aborted during synthesis, I will need the RTL files with XDC(whole project) to reproduce the issue. Please let me if this file with you so I can share an EZmove.

 

Thanks

Anusheel 

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