03-19-2018 12:13 PM
03-19-2018 10:59 PM
03-21-2018 10:41 AM
I just wonder why there is no clear message to indicate the reason when the FPGA synthesis job got aborted.
It would be hard to debug. There is quite a lot of constraints. How could we be sure that's the cause?
I tried vivado 2017.3.1 before. I got the same result. The question is why it's okay in 2014.4 but not in the later version?
03-25-2018 11:07 PM
I agree that such scenarios are hard to debug. Generally, Vivado writes errors and warnings in the log file for all the failures.
In this case, the tool is crashing while applying the XDC constraints hence I asked to check if there is any visible issue in XDC file.
Is it possible for you to share the design? I will share an EZmove link with you to share the files over secured channel.
03-27-2018 09:06 AM
That's would be great. Please let me know what files are needed. Is .dcp file good enough?
04-01-2018 11:07 PM
As the run was aborted during synthesis, I will need the RTL files with XDC(whole project) to reproduce the issue. Please let me if this file with you so I can share an EZmove.