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Observer zelalex
Observer
6,641 Views
Registered: ‎04-24-2012

FSM Designing : Synchronisation problem {USING VHDL language on Xilinx Ise 13.4}

I have designed a FSM for the control unit of  a coprocessor for matrix multiplication. I wish that some of the cases update at negative edge and some of the cases at the positive edges.

Mainly

 when s11 =>     s_count_p <= s_count_p + 1;
                                    s_count_m_2 <= 0;
                                    s_new_acc <= '0';
                                    state <= s9;

I wish this to work at positive edge.

The XST is not allowing this. How do I do this?

-----

The CODE is:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.ALL;
use work.Matrix_coproc_pack_v002.ALL;

entity Control_Unit_v002 is
    port (     CLK : in std_logic;
                START : in std_logic;
                K, M, P : in natural range 0 to (2**N)-1;
                RD_A, RD_B : out std_logic;
                COUNT_K, COUNT_M, COUNT_M_2, COUNT_P : out natural range 0 to (2**N)-1;
                NEW_ACC : out std_logic;
                TEMP : out state_type
            );
end Control_Unit_v002;

architecture Behavioral of Control_Unit_v002 is
    signal state : state_type;
    
    signal s_k, s_m, s_p : natural range 0 to (2**N)-1;
    signal s_count_k, s_count_m, s_count_m_2, s_count_p : natural range 0 to (2**N)-1 := 0;
    signal s_new_acc : std_logic;
    signal s_rd_a, s_rd_b : std_logic;
    
--    signal k_equal, m_equal, m_2_equal, p_equal : boolean;
    signal k_less, m_less, m_2_less, p_less : boolean;
begin
    TEMP <= state;

    COUNT_K <= s_count_k;
    COUNT_M <= s_count_m;
    COUNT_M_2 <= s_count_m_2;
    COUNT_P <= s_count_p;
    NEW_ACC <= s_new_acc;
    RD_A <= s_rd_a;
    RD_B <= s_rd_b;
    
--    k_equal         <= (s_count_k         = s_k);
--    m_equal         <= (s_count_m         = s_m);
--    m_2_equal     <= (s_count_m_2     = s_m);
--    p_equal         <= (s_count_p         = s_p);
--    
    k_less        <= (s_count_k         < s_k);
    m_less        <= (s_count_m         < s_m);
    m_2_less        <= (s_count_m_2     < s_m);
    p_less        <= (s_count_p         < s_p);
    
    State_Change : process(CLK, START)
    begin
        if(START = '1') then
            state <= s1;
        elsif(CLK'event and clk = '0') then
            case state is
            --s3, s4, s5 have the same state update if-else ladder
            --s7, s8, s9 have the same state update if-else ladder
                when s1 =>     s_k <= K;
                                s_m <= M;
                                s_p <= P;
                                
                                state <= s2;
                
                when s2 =>    s_rd_a <= '1';
                                s_rd_b <= '0';
                                s_new_acc <= '0';
                                s_count_k <= 0;
                                s_count_m <= 0;
                                
                                state <= s3;
                    
                when s3|s4|s5 =>  if(m_less) then
                                            s_count_m <= s_count_m + 1;
                                            
                                            state <= s4;
                                        else
                                            if(k_less) then
                                                s_count_k <= s_count_k + 1;
                                                s_count_m <= 0;
                                                
                                                state <= s5;
                                            else
                                            
                                                s_new_acc <= '1';
                                                
                                                state <= s12;
                                            end if;
                                        end if;
                                
                when s7|s8|s9 =>    if(m_2_less) then
                                            s_count_m_2 <= s_count_m_2 + 1;
                                            s_new_acc <= '0';
                                            
                                            state <= s8;
                                        else
                                            if(p_less) then
                                                s_new_acc <= '1';
                                                
                                                state <= s11;
                                            else
                                                s_rd_b <= '0';
                                                
                                                state <= s10;
                                            end if;
                                        end if;
                                
                when s10 =>
                
                when s11 =>     s_count_p <= s_count_p + 1;
                                    s_count_m_2 <= 0;
                                    s_new_acc <= '0';
                                    state <= s9;
                
                when s12 =>        s_rd_a <= '0';
                                    s_rd_b <= '1';
                                    s_count_m_2 <= 0;
                                    s_count_p <= 0;
                                    s_new_acc <= '0';
                                    state <= s7;
                
                when others =>
            end case;
        end if;
    end process;
end Behavioral;

sim1.png
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13 Replies
Advisor eilert
Advisor
6,631 Views
Registered: ‎08-14-2007

Re: FSM Designing : Synchronisation problem {USING VHDL language on Xilinx Ise 13.4}

Hi,

first of all, why are you working on the negative edge at all?

While it is possible, commonly everything works on the rising edge?

 

Then, mixing clock edges in an algorithm probably causes more trouble than the doubtful benefits that you might expect from this step. (Especially the timing between the differently triggered  FFs will become difficult.)

 

So what's the great thing that needs to happen so fast in State 11?

You are incrementing some conter and setting some signals to '0'.

Why can't you do this with the normal clock? It looks OK in your simulation.

 

Or is your problem something completely different and has nothing to do at all with the things happening in S11?

(e.g. taking over the data from S8: 1,3,1,3 vs. 2,4,2,4)

 

Have a nice synthesis

  Eilert

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Observer zelalex
Observer
6,626 Views
Registered: ‎04-24-2012

Re: FSM Designing : Synchronisation problem {USING VHDL language on Xilinx Ise 13.4}

@eilert


Hi,

first of all, why are you working on the negative edge at all?

While it is possible, commonly everything works on the rising edge?


I am designing a coprocessor.

I have designed it such that the processor will give the data and all signals on positive edge. Data and everthing resides for 1 clock cycle. I am using the data given from processor on -ve edge inside the coprocessor. So, effectively the thing will work on +ve edges for the processor and the user of the overall system.


Then, mixing clock edges in an algorithm probably causes more trouble than the doubtful benefits that you might expect from this step. (Especially the timing between the differently triggered  FFs will become difficult.)


The reason for working on different edges inside and outside of the coprocessor is because of synchronization. When I was using the +ve edge sometimes the coprocessor's modules took data from before the edge and sometimes from after the edge. I couldn't figure out what was happening so I chose to take data in the middle of 2 transitions( i.e. -ve edge of clk which is between 2 +ve edges of clk)  to besure of what's happening. That made my design easier for me to make. Much easier.


So what's the great thing that needs to happen so fast in State 11?

You are incrementing some conter and setting some signals to '0'.

Why can't you do this with the normal clock? It looks OK in your simulation.


The white waveform in the last line is clock.

The results are present but I need to extend the [20, 44..  and [14,30.. for half  more clock cycle.This is again so that I can use the data on -ve edge.

 

The reason I want to go fast is because the coprocessor is meant to be a optimal solution.


So, again with the main thing. Is there a way by which I can do the updating of some states of FSM at +ve clocks and some at -ve clocks?

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Historian
Historian
6,615 Views
Registered: ‎02-25-2008

Re: FSM Designing : Synchronisation problem {USING VHDL language on Xilinx Ise 13.4}

Your synchronization problems are the result of not understanding delta delays.

----------------------------Yes, I do this for a living.
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Teacher eteam00
Teacher
6,612 Views
Registered: ‎07-21-2009

Re: FSM Designing : Synchronisation problem {USING VHDL language on Xilinx Ise 13.4}

first of all, why are you working on the negative edge at all?

While it is possible, commonly everything works on the rising edge?


I am designing a coprocessor. I have designed it such that the processor will give the data and all signals on positive edge. Data and everthing resides for 1 clock cycle. I am using the data given from processor on -ve edge inside the coprocessor. So, effectively the thing will work on +ve edges for the processor and the user of the overall system.

 

There are some missing details.  If the processor and coprocessor are using the same clock timebase, but the clock and data skews are such that same-edge clocking is unreliable (setup/hold time uncertainty), then opposite-edge clocking may be a perfectly reasonable and effective design solution.  This is entirely analogous to SPI and JTAG interfaces which generate output data on one clock edge and sample input data on the oppposite clock edge.

 

If the processor and co-processor are not using the same clock timebase, and negative-edge clocking seems to work only because the logic simulation is incomplete or mis-applied, then full-on synchronisation is indeed required.

 


Then, mixing clock edges in an algorithm probably causes more trouble than the doubtful benefits that you might expect from this step. (Especially the timing between the differently triggered  FFs will become difficult.)


The reason for working on different edges inside and outside of the coprocessor is because of synchronization. When I was using the +ve edge sometimes the coprocessor's modules took data from before the edge and sometimes from after the edge. I couldn't figure out what was happening so I chose to take data in the middle of 2 transitions( i.e. -ve edge of clk which is between 2 +ve edges of clk)  to besure of what's happening. That made my design easier for me to make. Much easier.

 

Your explanation is far from clear.  You may be doing the right thing without properly understanding the reasons, or you may be flailing away at solutions which seem to work but are fundamentally flawed.  Without more details describing the source (processor) side of the interface, it is difficult to discern whether you are clever, lucky, or simply fooling yourself.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Instructor
Instructor
6,610 Views
Registered: ‎08-14-2007

Re: FSM Designing : Synchronisation problem {USING VHDL language on Xilinx Ise 13.4}

So, again with the main thing. Is there a way by which I can do the updating of some states of FSM at +ve clocks and some at -ve clocks?

 

The short answer is no.  You can have some signals that update on the rising edge and others that update

on the falling edge, but the same signal can only update on one edge or the other (unless you are targetting

a part like CoolRunner 2 with dual-edge flip-flops).

 

What I don't understand is why you think you need to do that.  Assuming any particular signal is sampled on

only one edge of the clock by the processor, then that signal should always change on the appropriate

clock edge when driven by the coprocessor.  If you really need opposite-edge clocking to avoid hold time

issues, then the appropriate edge would be the opposite clock edge.  However in a synchronous system

there is usually a way to ensure that there are no hold time errors when using the same clock edge, and

in that case you can usually run faster because of the additional setup time.

 

-- Gabor

 

 

-- Gabor
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Advisor eilert
Advisor
6,603 Views
Registered: ‎08-14-2007

Re: FSM Designing : Synchronisation problem {USING VHDL language on Xilinx Ise 13.4}

Hi,

you already got some good feedback feedback over night.

But let me ask some more questions:

 

Are the processor and coprocessor in one FPGA ore are they intended to be in two different devices?

In the first case all this negedge/posedge hassle is just bad.

In the second case it depends on the clock management between the devices.

 

The strange simulation results can be explained (bassmann already pinpointed the root cause).

Your simulation probably has statements like this in it:

 

wait for 100 ns;

input_signal  <= '1';

wait for 100 ns;

etc..

 

Now if the signal changes happen at the same time as the clock rises the results are unpredictable.

Within the delta cycles of the actual simulation time you can not say, wether the signal change happens before or after the active clock edge.

 

This can be overcome by using code like this (so you dont need to reconstruct your whole testbench)

 

wait until rising_edge(clk);

input_signal  <= '1';

wait until rising_edge(clk);

 

Now it's clear that the testbench has to wait until the clock has risen before the signal changes to 1.

That input value willl then be effective to the DUT at the next rising clock edge.

 

This code mimics the behavior of some registered output, so your waveform will look the same when you tie together the processor and your coprocessor.

 

A testbench should provide stimuli just the way that some attached design/IP would do.

Therefore, the processes in a testbench should also be synchronized to the clock.

However, additional short delays can be applied using wait-for or after statements if needed.

(e.g. to simulate routing or PCB-track delay)

 

 

 

So maybe you check your testbench setup for flaws and eliminate these before you apply changes to your designs that might not really help improving it.

 

Don't be bothered that hte people here are quite suspichious about your approach.

You're not the first who tries to do this, and in most cases this approach was wrong.

So please make sure that your setup works properly (testbench etc.) and that you give sufficient explanations about your designs background and a clear reasoning for your approach.

The people here surely can help you with muklti clock domain designs, communicating porocesses and such.

But it would be a timewaste for all (including you ) if this would be in vain because there might just be something wrong with your testbench setup.

 

Have a nice simulation

  Eilert

 

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Observer zelalex
Observer
6,592 Views
Registered: ‎04-24-2012

Re: FSM Designing : Synchronisation problem {USING VHDL language on Xilinx Ise 13.4}

I think I need to explain my problem again.

 

This is my first time making a big design which needs a control unit(THE FSM THAT I HAVE GIVEN IN MY FIRST POST) so I am certainly a beginner at taking care of synchronization problems.

 

@bassman59

I will look at my code from the point of view of delta delays. I had overlooked that.

 

@eteam00

Currently I am designing only the coprocessor. I am designing it assuming that it will work on the same clock as the processor with which it is going to be used.

 

Your explanation is far from clear.  You may be doing the right thing without properly understanding the reasons, or you may be flailing away at solutions which seem to work but are fundamentally flawed.  Without more details describing the source (processor) side of the interface, it is difficult to discern whether you are clever, lucky, or simply fooling yourself.


I think that may be correct.

There have been times when I used hit and trial to get simulation results. Not proud of it but I have done it. I got the results I wanted but I did not understand what was the synchronization problem in my design before I tweaked it.

 

there is usually a way to ensure that there are no hold time errors when using the same clock edge, and in that case you can usually run faster because of the additional setup time.

 

In theory I know that the problem can be solved by using single clock edge but as this design is a little bigger than I am used to I haven't been able to put theory into practice.

 

@eilert

I had made my testbench according to +ve edges but after reading your comment I checked again. There was a one single which was not according to +ve edge.

 

From now on, whenever I write testbenches I will always consider the advice you gave me.

 

 

THANK YOU ALL VERY MUCH.

Posting on this forum has been really helpful to me.

 

 


I solved the problem due to which I needed the state updating on different edges in my FSM  by tweaking my design. But, I think I will need some advice regarding taking care of synchronisation problems.

 

If anyone interested :

I am trying to implement the architecture of the coprocessor described here:

http://www.sciencedirect.com/science/article/pii/S0141933107000841

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Teacher eteam00
Teacher
6,589 Views
Registered: ‎07-21-2009

Re: FSM Designing : Synchronisation problem {USING VHDL language on Xilinx Ise 13.4}

This has already been asked, but not answered:

 

Are the processor and co-processor both resident on a single FPGA?  Or is the processor external to the FPGA?

 

Depending on your answer, there will be additional questions.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Observer zelalex
Observer
6,583 Views
Registered: ‎04-24-2012

Re: FSM Designing : Synchronisation problem {USING VHDL language on Xilinx Ise 13.4}

As of now there isn't a processor.

 

I am designing a coprocessor only and haven't implemented it on a FPGA yet.

I am using ISE till now for simulation by a pseudo bus interface(my test bench). I am using the pseudo bus interface as a component in my coprocessor and placed all my simulation requirements in that testbench.

 

But my preference would be to implement both processor and the coprocessor on the same FPGA.

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Advisor eilert
Advisor
3,371 Views
Registered: ‎08-14-2007

Re: FSM Designing : Synchronisation problem {USING VHDL language on Xilinx Ise 13.4}

Hi,

in that case (both components reside in the same FPGA):

Stay with one active clock edge, preferably the rising edge to be compatible with most available IP.

 

If you have problems with your simulation:

 - blame the testbench, it might behave wrong. (Who wrote that darn thing?)

 - blame yourself, you might lack some experience (But you are gaining some at that moment.)

 

What's this pseudo bus interface model that you are using?

Have you created it or has it been provided by some other source?

Do you have documentation/specs for it?

 

Maybe if you provide some informations about your testbench (source) it might help to identify further problems that you haven't even recognized yet.

 

Have a nice simulation

  Eilert

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Highlighted
Visitor 40818041
Visitor
3,029 Views
Registered: ‎10-20-2013

Re: FSM Designing : Synchronisation problem {USING VHDL language on Xilinx Ise 13.4}

HI
I want to create a new project with XPS xilinx and I want to use the APU interface to create a high-speed data stream .
I use virtex-5-ml507-powerpc and Xilinx ISE Version 12.1 .
now ,I just have a simple VHDL code for trying
please, I need your help
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Visitor 40818041
Visitor
3,028 Views
Registered: ‎10-20-2013

Re: FSM Designing : Synchronisation problem {USING VHDL language on Xilinx Ise 13.4}

HI
I want to create a new project with XPS xilinx and I want to use the APU interface to create a high-speed data stream .
I use virtex-5-ml507-powerpc and Xilinx ISE Version 12.1 .
now ,I just have a simple VHDL code for trying
please, I need your help

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Teacher eteam00
Teacher
3,027 Views
Registered: ‎07-21-2009

Re: FSM Designing : Synchronisation problem {USING VHDL language on Xilinx Ise 13.4}

This thread is very old and dormant.  Please use the thread you have already posted for your questions.

It is considered bad manners to pose the same question or problem in multiple threads -- this leads to confusion and duplication of effort.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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