Hi,
In Vivado 2020.1, the synthesizer fails to recognize an FSM, which I think is a bug.
This is a minimized version of an issue I encountered while working on a much larger design. I tried to minimize this code further by making small changes to it, but invariably this leads to the FSM recognition to succeed again. For example, getting rid of the 'else' case in the comments or changing 'IN2' in the S3 case to 'IN1' will make FSM recognition work again.
It is completely unclear to me why my particular code inhibits FSM recognition.
Is this a known issue?
Best, Sidney
library ieee;
use ieee.std_logic_1164.all;
entity toplevel is
port (
CLK : in std_logic;
IN1 : in std_logic;
IN2 : in std_logic;
OBSERVER : out std_logic
);
end entity toplevel;
architecture arch of toplevel is
type FsmState is (S1, S2, S3);
signal current_state : FsmState := S1;
begin
process (CLK) is
variable next_state: FsmState;
begin
if rising_edge(CLK) then
next_state := current_state;
case current_state is
when S1 =>
next_state := S2;
when S2 =>
if IN1 = '1' then
next_state := S3;
elsif IN2 = '1' then
next_state := S1;
else
-- Vivado recognizes an FSM if the assignment below is commented out.
-- Leaving it in prevents FSM recognition, even though it is functionally identical.
next_state := S2;
end if;
when S3 =>
if IN2 = '1' then
next_state := S1;
else
next_state := S2;
end if;
end case;
current_state <= next_state;
end if;
end process;
OBSERVER <= '1' when current_state = S1 else '0';
end architecture arch;
