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Visitor
Visitor
621 Views
Registered: ‎06-18-2020

FSM extraction "sequential" causes timing loop

Hi,

I am in the process of porting a working complex design from Altera Quartus to Xilinx Vivado. I am using a state machine to control access to a BRAM memory block. During synthesis, the FSM extraction applies the "sequential" encoding to my state register "cs". And suddenly, it reports a timing loop through "cs". Indeed there is a larger "loop" in the original design spanning multiple modules but it is actually broken by "cs" being a register.

If I use a different FSM extraction algorithm or disable it completely, no timing loop is reported and it synthesizes okay (haven't tried out on a physical board though).

I am afraid that I am not allowed to share the whole design and I am not sure whether I am able to produce a minimal example.

Did somebody else see this issue before? Since I am new to the Xilinx world, let me know if I can share some form of synthesis output to help investigating.

Thanks!

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Scholar
Scholar
601 Views
Registered: ‎08-01-2012

Without the code, there is little we can say. Why do you have a loop through several modules? why is it not pipelined more? How is CS created, is it in a clocked process?

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Visitor
Visitor
596 Views
Registered: ‎06-18-2020

The code of the FSM looks like this:

logic [1:0] cs, ns, ps;
localparam idle=2'b00, counting=2'b01, bursting=2'b10;
// Advance the finite-state machine
always_ff @ (posedge memclock) begin
	if (reset) begin
		{cs, ps} <= {idle, idle};
	end else begin
		{cs, ps} <= {ns, cs};
	end
end
// Compute next state
always_comb begin
	ns = cs;
	case(cs)
		idle:
			if (external_input) begin
				if (external_input2) begin
					ns = counting;
				end else begin
					ns = bursting;
				end
			end
		counting:
			if (...) begin
			       ns = bursting;
			end
		bursting:
			if (...) begin
				ns = idle;
			end
		default:
			ns = 'x;
	endcase
end

assign external_output = cs==bursting | ps==bursting | cs==idle & ps==counting;

cs is the current state, ns the next state, and ps the previous state. external_input does combinatorially depend on external_output. So cs is set in a clocked process, which in my opinion should break any combinatorial loop. Note that the synthesis result knows an entry "cs" and "cs_reg" as well - if this helps.

It is not pipelined more to not add more latency when reading the RAM (the "user" is a microprocessor core). Of course I could pipeline more, but I do not see a reason for this until now. It was never the longest path during timing analysis and there is also barely any computation going on between external_output and external_input (basically one bit signal just to decide whether the memory is no longer busy and I can trigger a new access as soon as possible).

P.S.: To make things even more spooky, in the process of porting, I added an unrelated (to the reported loop), rather large module (many LUTs) which suddenly made the timing loop disappear.

P.P.S.: I am rather certain that this is a bug in the FSM extraction, very unfortunately there is no option to file a bug report.

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Xilinx Employee
Xilinx Employee
488 Views
Registered: ‎05-14-2008

Which Vivado version are you using?

Indeed, without a test case, there is little we can do.

-vivian

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Visitor
Visitor
458 Views
Registered: ‎06-18-2020

I am using Vivado 2019.2.

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Visitor
Visitor
449 Views
Registered: ‎06-18-2020

Maybe you can offer a safe and secure way to upload a testcase?

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Xilinx Employee
Xilinx Employee
390 Views
Registered: ‎05-14-2008

Please check the private message and send me your email box.

Then I'll send you an EZMOVE link to send your test case which is safe and secure.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
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Voyager
Voyager
365 Views
Registered: ‎06-20-2012

@SH  synthesize with -flatten_hierarchy full

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