UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
7,041 Views
Registered: ‎08-29-2009

FSM not inferred

Hi,

I am a student trying to learn how to program FPGA's with VHDl. my design has many areas which I thought shold infer FSM's, however when I synthesized the entire project, only one inferred a FSM.  Could this just be optimization sincethey are simple or am I doing something wrong?

 

here is one example that once synthesized has an info message about one-hot encoding:

 

architecture Behavioral of select_cont is
type state_type is (a,b,c);
signal ss, xs: state_type; -- current state, next state


begin
sync_proc : process (clk)
 begin
  if rising_edge(clk) then
   ss <= xs;
  end if;
 end process sync_proc;

 

comb_proc : process (rset,sn)
 begin
  if (rset = '1') then
   xs <= a;
  elsif rising_edge(sn) then
   case ss is
    when a =>   xs <= b;
    when b =>   xs <= c;
    when c =>   xs <= a;
    when others =>   xs <= a;
   end case;
  end if;
 end process comb_proc;

 

 with ss select
  sn_out <= "00" when a,
      "01" when b,
      "10" when c,
      "00" when others;

 

end Behavioral;

 

 

Here is the synthessi report:
Synthesizing Unit <select_cont>.

Related source file is "C:/Users/Adam/Documents/sumFPGA/fpga programming/fridge_controller/reset_cont.vhd".

INFO:Xst:2117 - HDL ADVISOR - Mux Selector <ss> of Case statement line 0 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:

- add an 'INIT' attribute on signal <ss> (optimization is then done without any risk)

- use the attribute 'signal_encoding user' to avoid onehot optimization

- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization

Using one-hot encoding for signal <ss>.

Found 3-bit register for signal <ss>.

Found 3-bit register for signal <xs>.

Summary:

inferred 3 D-type flip-flop(s).

Unit <select_cont> synthesized.

 

 

Thank You for any comments or suggestions!

Tags (4)
0 Kudos
4 Replies
Xilinx Employee
Xilinx Employee
7,037 Views
Registered: ‎04-15-2008

Re: FSM not inferred

Hi soccerpall86,

 

Check out Chapter 3 in the XST User Guide. It describes coding techniques for creating a variety of common digital logic circuits including FSMs with one, two, or three processes.

 

From just glancing at your code, it probably has something to do with sn being treated as a clock due to the rising_edge keyword.  Most likely you want the whole if statement to be level sensitive and entirely combinatorial so that the only registers in the FSM are the state registers.  There may be other things I didn't catch, though, so check out Chapter 3 and follow the coding examples.

 

Good luck!

-Hobson

7,029 Views
Registered: ‎08-29-2009

Re: FSM not inferred

I think I understand what your saying about making the whole if statement level sensitive, however since I only want one state change everytime the sn signal goes high (from a debounced input). I geuss either would have to makea pulse or rewrite it  as what follows.  Is there a better way to do this?

 

signal temp        : std_logic:='0';

 

begin


sync_proc : process (clk)
 begin
  if rising_edge(clk) then
   ss <= xs;
  temp <= sn;
  end if;
 end process sync_proc;

 

comb_proc : process (rset,sn)
 begin
  if (rset = '1') then
   xs <= a;
  elsif temp = '0' and sn = '1' then
   case ss is
    when a =>   xs <= b;
    when b =>   xs <= c;
    when c =>   xs <= a;
    when others =>   xs <= a;
   end case;
   else xs <=ss;
  end if;
 end process comb_proc;

 

 with ss select
  sn_out <= "00" when a,
      "01" when b,
      "10" when c,
      "00" when others;

 

end Behavioral;

0 Kudos
Historian
Historian
7,006 Views
Registered: ‎02-25-2008

Re: FSM not inferred

DO NOT use the two-process state machine paradigm. That sort of process might be fine for the veteran who knows what he's doing, but they are an endless source of agita for the newbie.

 

Just use a single process that is sensitive to the global clock.

 

-a

----------------------------Yes, I do this for a living.
0 Kudos
Xilinx Employee
Xilinx Employee
6,998 Views
Registered: ‎04-15-2008

Re: FSM not inferred

Hi soccerpall86,

 

It looks like you're just doing a rising edge detect on sn, which is perfectly legitimate.  Generating a single cycle pulse based off of the edge detect is also valid, but adds an extra cycle of latency on that input.  Either method will work.  Just like most circuits, it comes down to whether you need lower latency (use the edge detect method) or a higher clock frequency (use the pulse method).  I'm guessing here, but I doubt you're trying to squeeze every last bit of speed out of the circuit and I doubt latency is a particularly big concern since the input is debounced, so really it just comes down to personal preference.

 

The subject of FSM design methodology can often become a religious discussion akin to whether VHDL or Verilog is the better language.  So, I'll just say that there are pros and cons to each methodology and that it's important to understand those pros & cons as well as the design requirements before selecting a methodology.

 

Regards,

-Hobson

0 Kudos