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Adventurer
Adventurer
9,185 Views
Registered: ‎11-09-2010

FSM synthesis problem

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hi,

I have a state machine in my VHDL code. As I saw EDK reports it is automatically implemented in 'On hot' method. Simulation was okey  also.

Sometimes at running , hardware crashed and after debugging  with chipscope I understand that the " one hot" FSM goes to undefined state "all zero" and never goes out of this state. I was already defined           

          when others => state_nxt <= init_state; 

but I think this line is ignored in "on hot" implementation.

 

I tried to find from which state, the FSM goes to "all zero" with chipscope but mysteriously the condition 

        ( state <> all zero ) && ( state_nxt = all zero )   

never triggered. ( this condition is okey because it is tested with other states of FSM ).

 

I don't know what happened,  the only think which I guess is a glitch on reset pin of FSM  flip-flops. Does anyone knows how should I solve problem?

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1 Solution

Accepted Solutions
Teacher eteam00
Teacher
11,895 Views
Registered: ‎07-21-2009

Re: FSM synthesis problem

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no, I used standard half-man model to define FSM

 

I am unfamiliar with term 'standard half-man model'.  Would you mind explaining the meaning and use of this model?  It would be much appreciated, if you don't mind.

 

Apparently you are using a 2-process state machine.  The segregation of the state register from the primary state machine logic does not remove the asynchronous input hazard.  If you have any asynchronous inputs to the process which generates the value thsns_state_nxt, this could well be a lockup problem for your state machine.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
10 Replies
Teacher eteam00
Teacher
9,180 Views
Registered: ‎07-21-2009

Re: FSM synthesis problem

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This response is not a direct answer to your question.

 

Do you have any asynchronous or unaligned inputs to your state machine?

In other words, are there any state machine inputs which are direct (unregistered) input signals?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Adventurer
Adventurer
9,177 Views
Registered: ‎11-09-2010

Re: FSM synthesis problem

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no, I used standard half-man model to define FSM

 

   
   SYNC_PROC: process (Bus2IP_Clk)
   begin
      if ( Bus2IP_Clk'event and Bus2IP_Clk = '1') then
         if (Bus2IP_Resetn = '0') then
            thsns_state    <= init_0;
         else
            thsns_state    <= thsns_state_nxt;
         end if;       
      end if;
   end process;
 

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Teacher eteam00
Teacher
11,896 Views
Registered: ‎07-21-2009

Re: FSM synthesis problem

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no, I used standard half-man model to define FSM

 

I am unfamiliar with term 'standard half-man model'.  Would you mind explaining the meaning and use of this model?  It would be much appreciated, if you don't mind.

 

Apparently you are using a 2-process state machine.  The segregation of the state register from the primary state machine logic does not remove the asynchronous input hazard.  If you have any asynchronous inputs to the process which generates the value thsns_state_nxt, this could well be a lockup problem for your state machine.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Teacher rcingham
Teacher
9,158 Views
Registered: ‎09-09-2010

Re: FSM synthesis problem

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"standard half-man model"

Is that half-man, half-biscuit?
:-)

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Historian
Historian
9,155 Views
Registered: ‎02-25-2008

Re: FSM synthesis problem

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@hamze wrote:

 

no, I used standard half-man model to define FSM

 

   
   SYNC_PROC: process (Bus2IP_Clk)
   begin
      if ( Bus2IP_Clk'event and Bus2IP_Clk = '1') then
         if (Bus2IP_Resetn = '0') then
            thsns_state    <= init_0;
         else
            thsns_state    <= thsns_state_nxt;
         end if;       
      end if;
   end process;
 


Please don't use two-process state machines. Use one synchronous process to describe them.

 

In the synthesis options, did you choose "Create safe state machine?" and if so, did you get a warning from the synthesizer, saying that "this version of the tools cannot guarantee a safe state machine?" There's a bug in the synthesizer that prevents it from creating such safe machines.

 

Do note that, as you suspect, when others => is ignored by the synthesizer. If you declare your states using an enumeration (the standard way), then by definition, you cannot have a state that is not in that list. Of course, in real hardware with one-hot coding, a four-state machine uses four bits, which means that there is a possibility that it can go into one of the 12 undefined states, which when others => should cover but it doesn't. (I filed a WebCase about this, and the support agent understood what I was asking, but he said that the synthesizer people disagreed with my suggestion that when others => should be used to define the safe state.)

 

 

----------------------------Yes, I do this for a living.
Adventurer
Adventurer
9,150 Views
Registered: ‎11-09-2010

Re: FSM synthesis problem

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you are right, I had a asyncronous signal which caused the problem, I think setup time and hold time was not considered.

I just put a register and now it is okey!

thanks

 

as I remember from university, standard model of implementing a sequential circuit like a state machine, consists of two part a combinational logic on top ( which determined mealy outputs and next_state signal ) and a memory part on below ( which usually are state flipflops ) , I hardly can remember that we called it halfman model.

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Historian
Historian
9,138 Views
Registered: ‎02-25-2008

Re: FSM synthesis problem

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@hamze wrote:

 

 

as I remember from university, standard model of implementing a sequential circuit like a state machine, consists of two part a combinational logic on top ( which determined mealy outputs and next_state signal ) and a memory part on below ( which usually are state flipflops ) , I hardly can remember that we called it halfman model.


As we've advocated before, burn those textbooks. For reasons that most professional FPGA designers don't understand, the universities insist on teaching essentially obsolete coding styles.

 

Back in the bad old days, when Synopsis' piss-poor FPGA synthesizer was the only option, it was too stupid to understand how to build a state machine from a single synchronous process. So the design guide had examples of the two-process machine -- one synchronous, which updated the machine outputs and created the current state register from a next-state register, and the second, combinatorial process, which decoded the states and assigned next outputs for the state register and whatever outputs your machine had. It was basically duplication of everything, because you needed a combinatorial-output signal for each machine output as well as the registered version, and same for the state register. And the killer was that you'd forget to assign some signal in a particular state in the combinatorial process and you'd get latches.

 

The single synchronous-process machine solves all of these problems. All modern synthesis tools have no problem with a single process. Yet the synthesis and style guides still show bad examples, and the university professors (who don't do this for a living) continue to preach from the same old texts.

 

While you're at it, forget the terms "Mealy" and "Moore" because they are irrelevant. All you care is that your machine inputs are synchronized to the clock, and that you decode the states and test some inputs, and if an output signal has to change, you change it, and if the state has to change, you change it.

----------------------------Yes, I do this for a living.
Teacher eteam00
Teacher
9,126 Views
Registered: ‎07-21-2009

Re: FSM synthesis problem

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I had a asynchronous signal which caused the problem, I think setup time and hold time was not considered.

 

It's not simply a matter of setup and hold time.  An unsync'ed input transition arrives at one FSM register input (e.g. thsns_state[1]) before a clock edge and arrives at another FSM register input (e.g. thsns_state[0]) after the same clock edge.  This happens because the path delays (logic and interconnect) from the async input to the various FSM registers are not uniform - some path delays are longer than others.  This will, of course, lead to state machine lockup.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Adventurer
Adventurer
9,116 Views
Registered: ‎11-09-2010

Re: FSM synthesis problem

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Thank you for you complete guide,

moreover sorry for misspell! It was "Huffman model" not "half-man model" ! There is a description of it in this pdf  http://www.eng.auburn.edu/~strouce/class/elec2200/elec2200-10.pdf

 

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Participant marco@ms
Participant
818 Views
Registered: ‎02-24-2016

Re: FSM synthesis problem

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@bassman59  Thank you for the confirm my understanding and stating it so cleary

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