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Scholar helmutforren
Scholar
232 Views
Registered: ‎06-23-2014

Failed to pass parameter from constraints file to top module

I'm using Vivado 2018.1 and SystemVerilog.

I recently found a post, that I can't seem to find right now.  I tried its suggestion, but it didn't work.  I'd really like to have it work.

Specifically, I have placed the following line in my constraints file:

set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value {-generic RESET_ACTIVE=0} -objects [get_runs synth_custom_board]

Meanwhile, my top module includes this code:

module My_Top#(
        parameter RESET_ACTIVE = 1             // FPGA_RESET_N is active 1=HIGH or 0=LOW
	)( ... )
...
if (RESET_ACTIVE == 1) begin
IBUF IBufRst (.I(FPGA_RESET_N), .O(ext_rst));
end else begin
IBUF IBufRst (.I(~FPGA_RESET_N), .O(ext_rst));
end
...
endmodule

So I had hoped that the constraints file set property would feed through to make my code sensitive to the opposite sense reset input.  But it didn't.  When I changed the module code to "parameter RESET_ACTIVE = 0", the reset behavior changed.  So I know my "if" statement is correct.  But when I changed the constraints file code "...{-generic RESET_ACTIVE=0}...", the reset behavior did NOT change.

I did take that constraints file set_property line and cut/paste it directly into the TCL window.  Indeed, it changed the property on this synth run.  So my custom synth run name is spelled correctly, and the set_property command in general is correct.

Does this strategy actually work at all from the constraints file?  If so, what am I doing wrong.  If not, is there a different way to do this?  I often have large and multiple code bases, running on different variants of boards.  In addition to reset sense, they may have other differences.  Since I'm already using the constraints file to customize the pinouts, it make great sense to customizse the sense of those pinouts too!

Thanks in advance for your help.

-Helmut

4 Replies
Moderator
Moderator
162 Views
Registered: ‎03-16-2017

Re: Failed to pass parameter from constraints file to top module

Hi @helmutforren , 

Try with command synth_design -generic RESET_ACTIVE=0 in tcl console directly. 

It will run synthesis. Then check you see the desired behaviour or not. 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Scholar helmutforren
Scholar
152 Views
Registered: ‎06-23-2014

Re: Failed to pass parameter from constraints file to top module

I ran many test cases to confirm that the concept works in the SystemVerilog code.  Then I set up a case with the constraints file having:

set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value {-generic RESET_ACTIVE=0} -objects [get_runs synth_custom_board]

yet the synth property itself had

-generic RESET_ACTIVE=1

So, the firmware behaved as if RESET_ACTIVE=1, meaning the constraints file did NOT override the synth property.  But when I copied that set_property command from the constraints file and pasted it into the TCL window, I checked and it did change the synth property itself to RESET_ACTIVE=0.  Subsequently the firmware behaved indeed like RESET_ACTIVE=0.  This means the set_property command is properly formed, but is NOT executing or overriding from the constraints file.  (Note that I previously tested with the synth property having no value for MORE OPTIONS, and so this is indeed a case of simply not working from the constraints file, as having to override.

Does this in fact just plain NOT WORK from the constraints file in Vivado 2018.1?

Is there a log somewhere that I can look to see what happened when this line of the constraints file was processed?

 

Thanks

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Explorer
Explorer
146 Views
Registered: ‎03-31-2016

Re: Failed to pass parameter from constraints file to top module

You can try changing the procesing order of the constraint to "EARLY" using properties  tab of that file in the project.  That might do what you want but the xdc is not intended as a replacedment for general TCL scripting.  The issue is that constraints are normally processed after elaboration when all the parameters/generics get defined.

You can do something similar using a pre-step tcl hook set on the synthesis run to execute a tcl script with a version of that command.  It will not be in the constraint file itself but that is probably the best you can do without a full custom build script.

Scholar helmutforren
Scholar
133 Views
Registered: ‎06-23-2014

Re: Failed to pass parameter from constraints file to top module

Thanks.  Early didn't work either.  I did have separate development auto-generating a pre-tcl script, so I adapted that and am now accomplishing my objective.


BTW, I thought the constraints file was a perfect place for this particular configuration parameter.  After all, the constraints file is used to specify which signal goes to which pin, and as such is custom for each FPGA/board setup.  Specifically, we were building for KC705 and AC701 and Custom Board.  All three have the cpu reset on a different pin, and the two dev boards are active high while the custom board is active low.  It made sense to specify the active level of the resets in the same place as the pin on which they reside.  But nope, it doesn't work.  

So for now, I've done this.  I already had four (not three) different synth runs with names like "synth_ac701_alphadata" and "synth_ac701_sundance", which were both for the AC701, but one using an AlphaData FMC_CAMERALINK card on my desk or a Sundance FMC Camera Link card on my associates desk.  (That's why four synth runs, not three.)  I my pre-tcl script was already creating an include file.  My top module was already including it.  I changed the pre-tcl script to add a [`define synth_ac701_alphadata] or other, and I have nested `ifdefs.  In there I now localparam RESET_ACTIVE.  Well, I must now define active sense in a different location from pin, but it works.

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