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Voyager
Voyager
597 Views
Registered: ‎06-20-2017

Feedback on ASYNC_REG in UG901 and UG912

Figure 3-1 of UG912 (linked to from UG901) shows a double flop for improving MTBF on asynchronous clock domain crossings.

 

However, @austin in this post recommends three register synchronizers, and provides great insight while doing so.

 

Consequently, updating figure 3-1 of UG912 would be a great way to more widely disseminate the recommendation to use three register synchronizers.  

 

Just a thought I thought I'd share.  Opinions may vary.   

Adaptable Processing coming to an IP address near you.
2 Replies
536 Views
Registered: ‎01-22-2015

Re: Feedback on ASYNC_REG in UG901 and UG912

In addition, Xilinx documumentation should someplace discuss the "perfect" double-flop synchronizer found in the IDDR and described by @avrumw in <this post>.

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Scholar ronnywebers
Scholar
517 Views
Registered: ‎10-10-2014

Re: Feedback on ASYNC_REG in UG901 and UG912

If they made their great courses a lot more cheaper, and in video format, available online, instantly and 24/7 (like it's 2018), yeah even with a monthly subscription, then we would have a lot less questions on how to get (basic) things done, and access to the latest information, on the latest Vivado version. I'm pretty sure they would have more turnover from their courses than they do now.

 

Take an example here, the best iOS tutorial site on the planet, started by one man a few years ago, for a price that you don't even blink an eye for.

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