File Integer read : size mismatch in assignment; read failed

[olivierhartmann]

Hello !

I try to fill an array from a file with integers. But why the "read(m_line, m_data)" function does not work when synthesizing : [Synth 8-5765] size mismatch in assignment; read failed.

Of course it works in simulation.

type info_bits_pos_t is array(0 to n_info_bits-1) of integer range 0 to n_encoded_bits-1;

impure function get_info_bits_pos(info_bits_file : string) return info_bits_pos_t is

	file     m_file : text open read_mode is info_bits_file;
	variable m_line : line;
	variable m_data : integer;
	variable ibp    : info_bits_pos_t;

begin
	for i in ibp'range loop
		assert not endfile(m_file) report "" severity failure;

		readline(m_file, m_line);
		read(m_line, m_data);

		ibp(i) := m_data;

	end loop;
	assert endfile(m_file) report "" severity warning;

	return ibp;
end function;

I also tried with 

variable m_data : integer range 0 to n_encoded_bits-1;

 but same results.

What's wrong ?

I can understand that an integer might be difficult to synthesis, but they are constraint. And more the issue appears when reading the file.

Thanks a lot.

Olivier

[brimdavis · Accepted solution]

@olivierhartmann "But why the "read(m_line, m_data)" function does not work when synthesizing"

Xilinx's older ISE XST synthesis tool had decent support for VHDL File I/O, which worked well for reading memory initialization files in various data formats[1].

Vivado synthesis VHDL File I/O is badly documented[2] and pretty much unusable.

[ note: last time I tried a ROM initialization function using a hex file reader was in Vivado 2015.x ]

-Brian

[1] XST file I/O is somewhat documented on pages 66-68 of

  ISE: UG687 - XST User Guide for Virtex-6, Spartan-6, and 7 Series Devices (ver14.5)

  See also:

    https://forums.xilinx.com/t5/Spartan-Family-FPGAs/Initializing-Block-RAM-with-External-Data-File/td-p/229193

  Generalized file parser that works with XST:

    https://github.com/VLSI-EDA/PoC/blob/master/src/mem/mem.pkg.vhdl

    https://github.com/VLSI-EDA/PoC/blob/master/src/mem/ocrom/ocrom_dp.vhdl

[2] Xilinx has deleted any mention of VHDL file I/O from Chapter 5 of their train-wreck Vivado synthesis manual:

  Vivado: UG901 - Vivado Design Suite User Guide: Synthesis (ver2017.2)

 They claim to support a limited (one binary ASCII string per line) file read for memory init (UG901 pages 148-149)

[olivierhartmann]

Hi @brimdavis !

Thank you for your quick message.

Then I'll use a bit_vector reader to fill unsigned value, instead of reading directly integers.

Thanks again.