01-20-2020 03:23 AM - edited 01-20-2020 03:23 AM
I'm testing the float_pkg library (IEEE-754 floating point standard) from VHDL-2008 in Vivado 2019.2 and Vivado 2018.3. I made just an addition between two numbers with a register in the output (Res <= A + B; inside a rising_edge(clk)).
Behavioral simulations are working properly but I noticed that HW utilization and time results were very good (maybe too much). Therefore, I made post implementation functional and timing simulations and the result of floating-point operations are not right.
For instance, in the case of an addition between 0x40000000 (that means 2.0 in IEEE-754) and 0x40600000 (3.5 in IEEE-754), - the result should be 0x40B00000 (5.5 in IEEE-754). However, the results that I get are:
I have tried the synthesis and implementation with two FPGAs from different families: xc7a35ticsg324-1L and xc7vx690tffg1761-3.
I also have tried the synthesis using Mentor Precision synthesizer and the post implementation simulations works properly. Then, I think it is a problem with Vivado synthesizer. Is this bug already known in Vivado?
I upload the code of the adder (adder.vhd), the testbench for behavioral simulation (adder_tb.vhd, using float32 signals) and the testbench for post-implementation functional simulation (adder_std_tb.vhd, using std_logic_vector signals because float32 signals are translated to std_logic_vector). As I say, the behavioral simulation works properly, but not the post-implementation simulation.
02-06-2020 08:59 PM
02-07-2020 01:04 AM
As a note - using the 2008 float library is unlikely to give very optimal results as the functions contain no pipelining. Does Xilinx have plans to get retimed registers working with floating point - or will they continue to push their floating point IP cores?
03-09-2020 01:59 AM