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Observer id314159
Observer
1,708 Views
Registered: ‎03-14-2018

Force LUT combinig?

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Dear Xilinx community,

 

I'm working on optimizing something as good as possible for the UltraScale+ fabric. At one point, I instantiate two LUT, one of which gets two inputs, the other gets four inputs, but both have one common input, i.e. in total, they require only 5 distinct inputs. In my understanding, this means that Vivado could combine both LUTs into a single LUT with 5 inputs, which uses both the O5 and O6 outputs. I included a template of that part of the code at the end.

 

However, when I implement my design, Vivado does NOT combine both LUTs into a single dual-output LUT.

 

I already found out about the "no_lc" option and people trying to prevent LUT combination, but is there any way to force Vivado to combine two LUTs? (I.e. something as a "DualLUT5"-primitive, attributes that must be set or so...)

 

Best regards

 

 

I_LUT2: LUT2
generic map(
    INIT    => "1110"
    )
port map(
    I0      => sig_a,
    I1      => sig_b,
    O       => res_a
    );
    
I_LUT4: LUT4
generic map(
    INIT    => "1111"&"1111"&"1111"&"1000"
    )
port map(
    I0      => sig_a,
    I1      => sig_c,
    I2      => sig_d,
    I3      => sig_e,
    O       => res_b
    );
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Mentor jmcclusk
Mentor
2,041 Views
Registered: ‎02-24-2014

Re: Force LUT combinig?

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I do this all the time, but I directly instantiate the LUT6_2 element, so there's no issue with Vivado trying to do something funny.  I put a DONT_TOUCH attribute on the LUT6_2 and that basically ends the argument.   Vivado implements it precisely, and I can even lock down (using LOCK_PINS) the specific pins on the LUT inputs, so that the router doesn't shuffle things around.  

 

Try using LUT6_2 and you'll be happy.   I also use BEL attributes to specify where in the slice to put it.   It's totally LOCKED DOWN!     I suppose if I was really compulsive I could lock down the routing, but I haven't bothered so far.

Don't forget to close a thread when possible by accepting a post as a solution.

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7 Replies
Moderator
Moderator
1,688 Views
Registered: ‎11-04-2010

Re: Force LUT combinig?

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Hi, @Anonymous ,
You can try LUTNM constraint described in UG903.
A unique string name applied to two LUTs to control their placement on a single LUT site. Unlike HLUTNM, LUTNM can be used to combine LUTs that belong to different hierarchical cells.
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Mentor jmcclusk
Mentor
2,042 Views
Registered: ‎02-24-2014

Re: Force LUT combinig?

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I do this all the time, but I directly instantiate the LUT6_2 element, so there's no issue with Vivado trying to do something funny.  I put a DONT_TOUCH attribute on the LUT6_2 and that basically ends the argument.   Vivado implements it precisely, and I can even lock down (using LOCK_PINS) the specific pins on the LUT inputs, so that the router doesn't shuffle things around.  

 

Try using LUT6_2 and you'll be happy.   I also use BEL attributes to specify where in the slice to put it.   It's totally LOCKED DOWN!     I suppose if I was really compulsive I could lock down the routing, but I haven't bothered so far.

Don't forget to close a thread when possible by accepting a post as a solution.

View solution in original post

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Observer id314159
Observer
1,656 Views
Registered: ‎03-14-2018

Re: Force LUT combinig?

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@jmcclusk: Thank you very much for that, I think that is precisely what I was looking for. I was already wondering because there is no such thing as a LUT6_2 primitive in the language template window in Vivado, where many of the primitives can be found... (At least not in the CLB branch and I could not find anything like this elsewhere.)

 

@hongh: Also thank you for your suggestion. Do I get it right that with this approach, I would have to specify the exact site of the LUT(-s)? (I.e. I cannot simply say "Put this wherever you want, but put both of these at the same site"?) Although this gives even a lot more control over the design, this seems a bit extreme for my current situation.

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Observer id314159
Observer
1,624 Views
Registered: ‎03-14-2018

Re: Force LUT combinig?

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Small update: Apparently there IS a LUT6_2 primitive even in the language template window, but only for basically any FPGA architecture other than UltraScale+. Is there any reason for that (no LUT6_2 directly instantiable) or is it simply missing the entry for the US+?
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Mentor jmcclusk
Mentor
1,608 Views
Registered: ‎02-24-2014

Re: Force LUT combinig?

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I wondered the same thing, so I quickly retargeted a project that uses LUT6_2 to the smallest Ultrascale+ device  (XCVU3P), and it seems to compile and route just fine.   So it appears to be an inadvertent exclusion in the language template.

 

The LUT6_2 is also in the Libraries Guide for Ultrascale, and there doesn't appear to be a separate library guide for Ultrascale+

 

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Moderator
Moderator
1,595 Views
Registered: ‎11-04-2010

Re: Force LUT combinig?

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Hi, @Anonymous , @jmcclusk ,
LUT6_2 is listed for all Ultra device and KU+ device in the language Template, but only missed for VU+ device in the language Template.
I think it is inadvertent exclusion and I'll reflect it to factory.
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Moderator
Moderator
1,401 Views
Registered: ‎11-04-2010

Re: Force LUT combinig?

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Hi, @Anonymous , @jmcclusk ,
LUT6_2 has been added for VU+ device in the language Template in the new version of Vivado .
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