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Adventurer
Adventurer
374 Views
Registered: ‎06-17-2015

Generics not evaluated before synthesis

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I am currently using Vivado 2018.1 for my project.
In my top level port I have the following generic:

entity TOP is
    generic(
        FIRMWARE_IS_CB       : boolean                       := false
    );

In the code I have 

gen_CB : if FIRMWARE_IS_CB generate
        read_pins_proc : process(clk_sys_100)
        begin
            if rising_edge(clk_sys_100) then
                if gclk_mngr_locked_100_le = '1' then
                    I2C_OE <= '1';
                end if;
            end if;
        end process;
end generate;

I use this on a regular basis to use a specific firmware across board that differ slightly in hardware. In this case, the board which has

FIRMWARE_IS_CB = false

does not have the top level port "I2C_OE".

However the synthesis will fail, reporting that the port is not present. Apparently the generate statement is not evaluated before this check is performed.

Can this be circumvented? How else can I achieve my goal?

BR Johannes

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Voyager
Voyager
280 Views
Registered: ‎04-26-2012

Re: Generics not evaluated before synthesis

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@cbhiskp   "However the synthesis will fail, reporting that the port is not present. "

Unlike C #ifdefs which ignore the enclosed code, VHDL generates require that the enclosed code be legal to compile - so any ports or signals referenced within the generate must exist in the design.

Conditionally created ports in VHDL can't be done with generates that I know of.

When I have to do something like this, I'll typically create a different top level wrapper for each of the hardware variants in use; this wrapper encloses the 'full' version with all the ports, some of which are unused/undriven for certain generic settings of this 'full' version. [ I think VHDL configurations can also be used for this sort of port remapping, but only if the tools support them ]

-Brian

6 Replies
Scholar richardhead
Scholar
350 Views
Registered: ‎08-01-2012

Re: Generics not evaluated before synthesis

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Are you sure the generic FIRMWARE_IS_CB  isnt being overridden by the project settings?

You can override the generics from TCL 

set_property generic "GENERIC=VALUE"
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Adventurer
Adventurer
345 Views
Registered: ‎06-17-2015

Re: Generics not evaluated before synthesis

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Thanks for your answer,

yes, as a matter of fact I do have some generics which I set before compilation with a TCL script

set COPPER_NOT_BASEX 1'b1

followed by the synthesis option

-generic COPPER_NOT_BASEX=$COPPER_NOT_BASEX

but this is not one of them.

In the log I see that the code is evaluated before the generics are:

ERROR: [Synth 8-1031] i2c_oe is not declared 

If I comment the line, I can see that it is evaluated correctly, and a bit later in the log this follows:

Parameter FIRMWARE_IS_CB bound to: 0 - type: bool 

I guess the problem is really the order in which code/generics are evaluated..

 

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Voyager
Voyager
281 Views
Registered: ‎04-26-2012

Re: Generics not evaluated before synthesis

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@cbhiskp   "However the synthesis will fail, reporting that the port is not present. "

Unlike C #ifdefs which ignore the enclosed code, VHDL generates require that the enclosed code be legal to compile - so any ports or signals referenced within the generate must exist in the design.

Conditionally created ports in VHDL can't be done with generates that I know of.

When I have to do something like this, I'll typically create a different top level wrapper for each of the hardware variants in use; this wrapper encloses the 'full' version with all the ports, some of which are unused/undriven for certain generic settings of this 'full' version. [ I think VHDL configurations can also be used for this sort of port remapping, but only if the tools support them ]

-Brian

264 Views
Registered: ‎01-08-2012

Re: Generics not evaluated before synthesis

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A really ugly (but possibly effective) way of dealing with this is to retain the I2C_OE output in the entity port declaration, and use an XDC constraint to map it to an I/O pin that is either unbonded or not connected on your PCB.

For my own designs that suffer from this sort of thing, I do what @brimdavis suggests and write a different top level wrapper for each of the hardware variants.

Scholar richardhead
Scholar
254 Views
Registered: ‎08-01-2012

Re: Generics not evaluated before synthesis

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@brimdavis

It is legal to have ports that are arrays with no declared size (since VHDL '93). This way they are sized on port mapping. Because VHDL allows zero length arrays, you can effectively remove the port.

 

entity some_ent is
port (
  port0 : std_logic_vector
);

signal zero_len_sig : std_logic_vector(0 downto 1);

inst : entity work.some_ent
port map (
  port0 => zero_len_sig
);

  

Note: There is currently a bug in Vivado where if PORT0 is a record type, if it is connected to something where one field of the record has zero length, the whole record is removed (very annoyingly!!!)

Adventurer
Adventurer
243 Views
Registered: ‎06-17-2015

Re: Generics not evaluated before synthesis

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@allanherriman @brimdavis @richardhead Thank you all for your answers and suggestions. 

The top level wrapper indeed seems to be the solution to my problem, it didn't occur to me.

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