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Explorer
Explorer
10,064 Views
Registered: ‎04-20-2010

Getting type values to show names during simulation?

If I define a type and signal like this:

 

type cpu_state_t is (INIT, FETCH, DECODE, EXECUTE);

signal cpu_fsm_t : cpu_state_t;

 

When I run a simulation the cpu_fsm_t signal displays with the defined type, i.e. INIT, DECODE, etc. shows up in the wave form display.  This is really nice and helps a lot with testing and troubleshooting.  Is there some way to do the same thing with values that are specifically defined?

 

For example, I know this is not possible, but reflects what I'm trying to do:

 

type mar_sel_t is (PC="00", ALU="01", T1="10", T2="11");

signal mar_sel_r, mar_sel_x : std_logic_vector(1 downto 0);

 

signal microcode : std_logic_vector(7 downto 0) := "0000" & PC & "00";

 

mar_sel_x <= microcode(3 downto 2);

 

if rising_edge(clk) then

  mar_sel_r <= mar_sel_x;

 

I would like to see mar_sel_r show up in the simulation wave from with the type names like PC, ALU, etc. instead of "00", "01", etc.  Right now I'm using constants, which works fine on the HDL side, but shows up as the binary values in simulation.

 

Thanks,

Matthew

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Explorer
Explorer
9,949 Views
Registered: ‎09-07-2011

A few ways to do it.    Maybe easiest is to make two conversion functions...

function to_slv  ( cpu : cpu_state_t) return std_logic_vector;
function to_cpu ( slv : std_logic_vector(1 downto 0)) return cpu_state_t;

signal microcode : std_logic_vector(7 downto 0) := "0000" & to_slv(PC) & "00"; signal mar_sel_r : std_logic_vector(1 downto 0); signal mar_sel_r_debug : cpu_state_t; .... process (clk) begin if rising_edge(clk) then mar_sel_r <= mar_sel_x; end end process; -- just for waveform debug mar_sel_r_debug <= to_cpu(mar_sel_r);

The functions can take advantage of the VHDL 'POS and 'VAL attributes, or use an explicit case statement to map numbers to names and vice versa.   Not sure if ISE and Vivado support the attributes.  

 

function to_slv ( c : cpu_state_t) return std_logic_vector is
     use ieee.numeric_std.all;
begin
     return std_logic_vector(to_unsigned( cpu_state_t'pos( c ) , 2));
   -- case c is
   --  when PC  => return "00"
   --  when ALU => return "11"
-- .... -- end case; end function; function to_cpu ( slv : in std_logic_vector) return cpu_state_t is use ieee.numeric_std.all; begin return cpu_state_t'val ( to_integer(unsigned(slv)));
-- case slv is
-- when "00" => return PC
-- .... end function;

 

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