07-24-2019 07:17 AM - edited 07-24-2019 07:18 AM
When I try to implement my desing, appears next:
In synthesis view, I see that LUTs usage is about 94%, and I think that is my problem. I am trying to reduce these number. About this 94%, I have been able to find out that 70% is the fault of a mathematical operation that I do many times, and it is a mapping function. I have attached two files (hey belong to an IP block that I have repeated many times), where I do the operation that I have mentioned.
Hope you can help me!
07-24-2019 07:29 AM
why you using std_logic_unsigned ?
if its a PWM , where is the clock ?
07-24-2019 07:32 AM
07-24-2019 07:44 AM
Your file is all combinational so I have no idea of what timing you require.
All I can suggest is instead of adding multiple instances of this file as it stands is to modify it where a single instance is capable of processing multiple results. For example if you need a result wihin 100nS then you could clock your algorithm at 100MHz and sequence 10 calculations through it. This would then reduce your logic to 1/10th of the current size.
07-24-2019 07:50 AM
My problem, right now, isn't with timing, it is about the number of LTUs used to implement the function to obtain the mapped number (pwm_map1). Removing this function, the LTUs usage is 17%. Any advice to change this function (line 80 of PWM_Manager_Core.vhd)?
07-24-2019 08:16 AM
clock the process,
then over smaple.
07-24-2019 08:42 AM
You cannot throw an algorithm like that at an FPGA without some thought. Your current file looks like a direct conversion into the vhdl language from a 'C' function.
FPGA design revolves around the usage of clocks. Seeing a file that is all combinational (particularly a file where it's doing an algorithm of a whole series of mults/divisions/Muxes etc.) sets off warning bells. And yes, I’m sure line 80 is the bulk of your LUT usage.
You need to introduce a clock into your design, you need to use that to break up your algorithm into steps using clocked registers, you need to consider logic reuse which is what I was describing above. This is how you will reduce your LUT usage.
Or, you could just reduce your bus widths (and dynamic range) by 50% which will reduce logic usage by 50% and stick with being all combinational if that’s what you really want..
07-24-2019 10:50 PM
Thank you very much. Yes, I am a c/c++ programmer and I an a newbie with FPGAs. I will think about how to introduce a clock into the system and do it as you tell me. Any advice?
07-25-2019 01:46 AM
a) forget programming languages, RTL is a hardware description language,
b) programming assumes a single processor, running fats, FPGAs get there speed by massive parallel and pipe lining
c) First understand what hardware / logic you want , then code to produce it.
Most important, ...... Get a good book on FPGAs / VHDL .... and go through the examples your self.
07-25-2019 03:07 AM
The only other advice I can offer other than DrJohnSmith's above is that you also consider using Vivado HLS which is basically a C/C++ to gates tool. There are loads of documents covering the subject available here and also a separate area on the Xilinx forums dedicated to HLS.