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gstorto
Visitor
Visitor
1,999 Views
Registered: ‎08-11-2017

Help with [Synth 8-5550] found explicit dontcare in slice;

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The following design was added to my project:

 

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test_dont_care is
    port (
        sel    : in std_logic_vector(1 downto 0);
        output : out std_logic_vector(7 downto 0)
    );
end test_dont_care;

architecture rtl of test_dont_care is
    type FIELD_ARRAY_TYPE is array (integer range <>) of std_logic_vector(7 downto 0);
    type EXT_FIELD_ARRAY_TYPE is array (integer range <>) of FIELD_ARRAY_TYPE (0 to 1);
    constant EXT_FIELD_ARRAY : EXT_FIELD_ARRAY_TYPE(0 to 1) := (("11110000", "00001111"),
                                                                ("XXXXXXXX", "XXXX1111"));

    signal array_1d_tmp : FIELD_ARRAY_TYPE(0 to 1);
begin
    array_1d_tmp(0 to 1) <= EXT_FIELD_ARRAY(to_integer(unsigned(sel(0 downto 0))));
    output <= array_1d_tmp(to_integer(unsigned(sel(1 downto 1))));
end rtl;

It basically selects a 2D array element using sel[0] for the row and sel[1] for the column indexes.

When I synthesize with Vivado 2017.3.1 the design, a critical warning concerning the don't care appears:

 

CRITICAL WARNING: [Synth 8-5550] found explicit dontcare in slice;  simulation mismatch may occur [...test_dont_care.vhd]

However, when the following patch is applied to the code:

 

16c16
<                                                                 ("XXXXXXXX", "XXXX1111"));
---
>                                                                 ("XXXXXXX0", "XXXX1111"));

No critical warning is reported in Vivado log. I have checked the schematics and the don't care seems correctly applied.

I have the following questions:

 

  1. Designs before and after patch are affected by simulation mismatch, so why is the second one not flagged?
  2. The don't care gives more freedom to the synthesizer on optimizing the design. Is it really a bad practice worth to be flagged as a Critical Warning?
  3. Is there a way to fix this message without increasing complexity of optimization?
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Accepted Solutions
aher
Xilinx Employee
Xilinx Employee
2,356 Views
Registered: ‎07-21-2014
Hi,

It looks like partial initialization of element of array to 'X' causes the CW to disappear. I have reported this as a bug.

-Shreyas
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4 Replies
aher
Xilinx Employee
Xilinx Employee
1,915 Views
Registered: ‎07-21-2014
Hi,

With patch do you mean you initialized 'EXT_FIELD_ARRAY' with value
(("XXXXXXXX", "XXXX1111"), ("XXXXXXX0", "XXXX1111"))?
In that case I tried with the patch but got the same critical warning in second case as well. Can you also post your code with patch to compare at my end.
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richardhead
Scholar
Scholar
1,908 Views
Registered: ‎08-01-2012

First of all, 'X' in VHDL is NOT dont care. It is Unknown. '-' is explicit dont care. But the synth tool is likely to treat is as dont care.

The warning likely comes because in RTL simulation, you will get explicit 'X' in the waveform. But in a netlist simulation and on the real hardware, you will get '1' or '0'. So if your testbench was set up to check for 'X', then you would get a missmatch.

To answer the questions:
1. I dont know. Maybe the circuit got optimised away and this LUT loogic was not left in, and hence the Xs go away. These errors also likely come as your arrays cannot be put into memory, so are generated in logic.
2. Yes it does give it the option. I generally dont use it though, and I have a rule I dont like seeing Xs on the wave form for valid data (if I have a design with byte enables, I will often fill invalid bytes with XXs, so that if they ever show up on a valid bus, I know something has gone wrong).
3. The warning is about simulation/synthesis missmatch, which is a valid warning (as I already pointed out).

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gstorto
Visitor
Visitor
1,881 Views
Registered: ‎08-11-2017

@aher The code that presents no critical warning is the following:

 

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test_dont_care is
    port (
        sel    : in std_logic_vector(1 downto 0);
        output : out std_logic_vector(7 downto 0)
    );
end test_dont_care;

architecture rtl of test_dont_care is
    type FIELD_ARRAY_TYPE is array (integer range <>) of std_logic_vector(7 downto 0);
    type EXT_FIELD_ARRAY_TYPE is array (integer range <>) of FIELD_ARRAY_TYPE (0 to 1);
    constant EXT_FIELD_ARRAY : EXT_FIELD_ARRAY_TYPE(0 to 1) := (("11110000", "00001111"),
                                                                ("XXXXXXX0", "XXXX1111"));

    signal array_1d_tmp : FIELD_ARRAY_TYPE(0 to 1);
begin
    array_1d_tmp(0 to 1) <= EXT_FIELD_ARRAY(to_integer(unsigned(sel(0 downto 0))));
    output <= array_1d_tmp(to_integer(unsigned(sel(1 downto 1))));
end rtl;

@richardhead Sorry for the confusion between "unknown" and "don't care". About answer #1, I thought it was the case, but the synthesized design in both cases result in the same design. I have checked and the INIT value of the LUT is the same.

You are right it is a mismatch, but being flagged as a critical warning seems a little bit excessive for me.

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aher
Xilinx Employee
Xilinx Employee
2,357 Views
Registered: ‎07-21-2014
Hi,

It looks like partial initialization of element of array to 'X' causes the CW to disappear. I have reported this as a bug.

-Shreyas
----------------------------------------------------------------------------------------------
Try to search answer for your issue in forums or xilinx user guides before you post a new thread.

Kindly note- Please mark the Answer as "Accept as solution" if information provided solves your query.
Give Kudos (star provided in right) to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

View solution in original post