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Visitor
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Registered: ‎05-19-2016

How to constrain output of BUFGMUX?

BUFGMUX

As shown, module1 and module2 are need synchronous, module3 and module2 are also need synchronous in the FPGA environment. How do I constraint my design?

In my current results, STA's report doesn't show the violation from Module1 to module2, but the function is obviously wrong, but also can identify Timing issues.

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Moderator
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Registered: ‎07-01-2015

Hi @wdpanjing,

 

Depending on BUFGMUX selector module2 will operate in either 150MHz or 70MHz.

Say module2 is operating at 150MHz and you are using Vivado then the path for module2 will be analysed both for 150MHz as well as 70MHz. In Vivado tool will analyze the interclock path i.e.; between 70MHz and 150MHz for module2. If you think both the clock domain are asynchronous then you can write constraints for:

  1. Create clock for 70MHz
  2. Create clock for 150MHz
  3. Asynchronous relationship between 70MHz and 150MHz clock.
Thanks,
Arpan
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Visitor
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Registered: ‎05-19-2016

hi @arpansur

  Thank you for you help.

  clk1 and clk2 are asynchronous and from different PLL.

  Tool:Synplify(for sythesis) + ISE(for par)

  Device:Vertex-5

  Constraint file:.ucf(for locations) and .sdc(clock constraint)

  I have:

   create clk1 for 150M

   create clk2 for 70M

   declare asynchronous relationship between them

 How does the tool know which clock to select to constrain module2 ?

Thanks!

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Xilinx Employee
Xilinx Employee
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Registered: ‎09-20-2012

Hi @wdpanjing

 

Refer to these AR's

 http://www.xilinx.com/support/answers/52788.html

http://www.xilinx.com/support/answers/7221.html

Thanks,
Deepika.
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Moderator
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Registered: ‎07-01-2015

Hi @wdpanjing,

 

As the clock would be dependent on BUFGMUX selector, tool will do analysis for both the clock domains and each will act as intaclock for module2. If module2 timing passes for both the clock domains then it won't be an issue when any of these 2 frequencies are selected using selector lines. 

Are you not seeing timing analysis for module2 for both the clock domains?

Thanks,
Arpan
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Visitor
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Registered: ‎05-19-2016

Hi @arpansur

 I don't know how to see timing analysis for module2? Form .twr file?

 

 I have tried tie BUFGMUX selector to 1. Then output of BUFGMUX is 150M. In the twr file I can see the violations path between module1 and mudule2. But when removing the tie of selector the violations is missing.

 So I guess module2 select the clk2(70M) for its constraint clk.

 

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Moderator
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Registered: ‎07-01-2015

Hi @wdpanjing,

 

Can you please attach the .twr file?

Thanks,
Arpan
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Visitor
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Registered: ‎05-19-2016

sorry,I can for some reason. Can you tell me how to use the fast clk1(150M) to constrain module2?
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Guide
Guide
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Registered: ‎01-23-2009

As the clock would be dependent on BUFGMUX selector, tool will do analysis for both the clock domains and each will act as intaclock for module2. If module2 timing passes for both the clock domains then it won't be an issue when any of these 2 frequencies are selected using selector lines. 

 

Infortunately, in ISE, this is not the case (it is, however, mostly true for Vivado). ISE was notoriously weak in working with gated clocks (among other things). In ISE, a wire can carry one and only one clock. When it comes to a BUFGMUX, only one of the two clocks will end up getting propagated on the output of the BUFGMUX. Which one can be somewhat difficult to predict - but you cannot count on it being the faster one. Furthermore, since this is static timing analysis (not dynamic) there is no "value on the selector"; this can (for example) come from logic, and hence is dynamic. Even if it is static (which would be pointless), the tools would still not propagate this constant to the selector - ISE simply has no mechanism for doing that.

 

The way to have the tools decide which clock gets propagated is to use the PRIORITY keyword on the clock creation, as was (sort of) described in the first answer record posted by @vemulad. However, there are (at least) 2 errors in this answer record (which is pretty unforgivable).

 

First, there is a typographical error; the first timespec should read

 

TIMESPEC "TS_clk_mux_up_1" = PERIOD "clk_mux_up" 8 ns HIGH 50% PRIORITY 1;

 

Since the text refers to that timespec.

 

But way more importantly it has the direction of the PRIORITY keyword backwards. From the constraints user guide (UG625 v14.5 p.201) "The lower the value, the higher the priority."

 

Thus, if you want TS_clk_mux_up_1 to win, then it must have a higher priority, therefore a lower value on the priority keyword. When unspecified the priority is 0, so you would need to use a negative number to raise the priority of this timespec - so it should be

 

TIMESPEC "TS_clk_mux_up_1" = PERIOD "clk_mux_up" 8 ns HIGH 50% PRIORITY -1;

 

Avrum

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Guide
Guide
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Registered: ‎01-23-2009

My previous post shows how to force the constraint of module 2 to 150MHz (using the PRIORITY) keyword.

 

However, I have a couple of other observations...

 

First, I assume that there is a BUFG on the paths to modules 1 and 3. Any BUFG on these lines should be parallel to the BUFGMUX (not in series with it - i.e. the two clock inputs should not already come from BUFGs) - cascading BUFGs (and a BUFGMUX is just a kind of BUFG) is generally a bad idea.

 

Now we have the bigger problem. Are there paths between module 1 and module 2 and also paths between module 2 and module 3? If so, then this are really difficult to constrain in ISE.

 

If you force the 150MHz clock to be used for the output of the BUFGMUX using the PRIORITY  (and have the BUFG for module 1 in parallel with the BUFGMUX) then the paths between modules 1 and 2 will be timed normally. However, the paths between modules 2 and 3 will be timed as if they were crossings between asynchronous domains. In ISE, all clocks are unrelated by default, and hence these paths simply won't be timed (if the clocks are described independently - i.e. the timespec of one isn't derived from the timespec of the other). Therefore, it will be up to you to manually constrain these paths - the easiest way to do this is using a FROM TO TIMESPEC on these paths - this would be something like

 

NET <output_of_BUFG_for_module3> TNM = "tnm_module3";

NET <output_of_BUFGMUX> TNM = "tnm_module2";

TIMESPEC TS_mod2_mod3 = FROM tnm_module2 TO tnm_module3 14.3ns;

TIMESPEC TS_mod3_mod2 = FROM tnm_module3 TO tnm_module2 14.3ns;

 

(I haven't tried this recently, and there could be errors, but this should be a good start to the problem).

 

Avrum

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Visitor
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Registered: ‎05-19-2016

Hi @avrumw

  Firstly, thank you for replying. What you think is right. I will try the two ways.

1) Both module1 and module 3 have a BUFG

2) There is paths between module1 and module2, also module2 and module3

3) clk1 and clk2 are asynchorous and from different PLLs.  

show you the entire picture. Red line means the data path. The BUFGMUX and the data path mux use the same selector.

20160521002158.png

 

 

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Visitor
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Registered: ‎05-19-2016

Hi @avrumw

Hi @arpansur

Hi @vemulad

  I have try the methods,but none works. I doubt whether I have the wrong constraint or the BUFGCE and BUFG directly connected to the PLL have an effect ?

1) set clk1 PRIORITY 1 and clk2 PRIORITY 2

  Constraints in the sdc file:

   define_clock {BUFGCTRL} -name {clk1} -freq 150;

   define_clock {BUFGCE} -name {clk2} -freq 70;

   define_attribute {BUFGCTRL} {syn_clock_priority} {1};

   define_attribute {BUFGCE} {syn_clock_priority} {2};

2) set clk1 PRIORITY -1 in the sdc file, but in the result file of synplify synthesis there is no PRIORITY constraint found.

  Constraints in the sdc file:

   define_clock {BUFGCTRL} -name {clk1} -freq 150;

   define_clock {BUFGCE} -name {clk2} -freq 70;

   define_attribute {BUFGCTRL} {syn_clock_priority} {-1};

3) use the FROM TO constraint to constrain between module2 and module3  

  Constraints in the sdc file:

   define_clock {BUFGCTRL} -name {clk1} -freq 150;

   define_clock {BUFGCE} -name {clk2} -freq 70;

  Constraints in the ucf file:

   NET "out_of_BUFGMUX" TNM_NET = "to_module2";

   NET "out_of_BUFG_to_module3" = "to_module3";

   TIMESPEC "TS_M2_to_M3" = FROM "to_module2" TO "to_module3";

   TIMESPEC "TS_M3_to_M2" = FROM "to_module3" TO "to_module2";

   

QQ20160523112022.png

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Guide
Guide
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Registered: ‎01-23-2009

It appears you are trying to constrain the system through Synplify. Most of the expertise you will find on the forums are for Xilinx tools. The information on PRIORITY and FROM TO constraints I gave you were for the UCF file...

 

I would suggest you focus on the implementation constraints in the UCF file. If you can get those constraints to work and pass timing, then the constraints for synthesis are less important.

 

Also, I note that the FROM TO constraints you have in your previous post don't have a time value - I don't know what that means (and I would have thought that they were illegal...)

 

Avrum

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