cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
e_heinz
Visitor
Visitor
944 Views
Registered: ‎07-02-2019

How to prevent using block RAM for inferred cells

Jump to solution

Hi,

I have a problem with Vivado (v2018.3) which sometimes infers block RAM for part of a logic which mostly consists of LUT lookups and some pipelining stages. The choice for block RAM appears to be random - some other time the same VHDL code is synthesized as registers.

The problem is: in case of block RAM synthesis, the timing fails. If register logic is used, the timing is ok.

So I tried to avoid using block RAM using constraints:  set_property RAM_STYLE DISTRIBUTED [get_cells *]

This has no effect, however. Probably, since the cells which are implemented as block RAM have no directly related source in the HDL code. They are created by Vivado during synthesis and have names like sel__9 or sel__7__2. So may be they do not exist at the time when the constraint is evaluated and therefore are not affected by the constraint?

What else can I do to avoid the usage of block RAM?

Thank you, and best regards,

Erik Heinz

 

0 Kudos
1 Solution

Accepted Solutions
hongh
Moderator
Moderator
931 Views
Registered: ‎11-04-2010

You can try to set  -max_bram option of Synthesis.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

4 Replies
hongh
Moderator
Moderator
932 Views
Registered: ‎11-04-2010

You can try to set  -max_bram option of Synthesis.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

richardhead
Scholar
Scholar
896 Views
Registered: ‎08-01-2012

Have you tried using the ramstyle attribute in your VHDL where the RAMs are inferred?

attribute ram_style : string;
attribute ram_style of myram : signal is "distributed" 

 

0 Kudos
surajc
Moderator
Moderator
874 Views
Registered: ‎01-30-2019

Hi @e_heinz 

Along with the above suggestions, I would suggest you to open elaborated design -> locate the ram cells -> use this name of ram cells in the RAM_STYLE constraint.

but as @richardhead mentioned it is always recommended to use RTL ram_style attribute to control the ram inference. 

0 Kudos
e_heinz
Visitor
Visitor
815 Views
Registered: ‎07-02-2019

Thanks for all the responses.

-max_bram did the trick. At least after I had figured out that I have to apply it by using

set_property STEPS.SYNTH_DESIGN.ARGS.MAX_BRAM <N> [get_runs synth_1]

in my TCL-based project (<N> is the option for -max_bram). There is no fine control, though, but for the moment it does all I need.

The RAM_STYLE constraint has no effect. I guess this is because when xdc files ar read the first time during elaboration, the cells in question do not exist yet. When xdc files are read the second time during implementation, synthesis is done and the decision for RAM style is made. But I may be wrong.

As for using the ram_style attribute in VHDL, there is no corresponding signal in the VHDL code for the cells in question, since they are created by Vivado. So I do not know to which signal I should apply this attribute.

Best regards,

Erik

 

0 Kudos