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Adventurer
Adventurer
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Registered: ‎03-13-2019

How to use 125mhz clock from KCU116 ?

Hello guys,

I am facing the issue in using 125MHz clock from KCU116 pin.

I had looked into the user guide of KCU116 and connected the 125 MHz pin from the user guide 
https://www.xilinx.com/support/documentation/boards_and_kits/kcu116/ug1239-kcu116-eval-bd.pdf (page number 29)
CLK_125MHZ_P LVDS G12
CLK_125MHZ_N LVDS F12

I want use this clock as a source clock for microblaze system. 
But during bit stream generation stage i got DRC error

[DRC NSTD-1] Unspecified I/O Standard: 2 out of 5 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: DIFF_CLK_125Mhz_clk_n, and DIFF_CLK_125Mhz_clk_p.


Later I checked this issue in many forum and checked this guide 
https://www.xilinx.com/support/documentation/user_guides/ug572-ultrascale-clocking.pdf (page 10)

But I am not able to understand this. Please anyone who knows this concept explain here.


How can I use the 125MHz clock in the design? 
Can I use this clock directly without using Clocking wizard?

Thank you
regards
Pavan Hegde



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6 Replies
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Registered: ‎06-21-2017

Do you assign pins in a xdc file?  You need to assign the IO standards in this file.  For instance:

set_property PACKAGE_PIN Y5 [get_ports MyClock_p]
set_property IOSTANDARD LVDS [get_ports MyClock_p]
create_clock -period 8.000 -name MyClock_p -waveform {0.000 4.000} [get_ports MyClock_p]
set_property DIFF_TERM_ADV TERM_100 [get_ports MyClock_p

This assigns the clock port to pins, tells Vivado that this is an LVDS signal and creates a timing constraint for the clock.  In this case, it also tells Vivado to use the internal termination resistor for the LVDS pair.  You need to check your schematic to see if there is already a resistor there, in which case you don't need this.  You also need to verify that the bank is powered by a VCCO voltage that allows the use of the internal resistor.

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Adventurer
Adventurer
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Registered: ‎03-13-2019

Thank you for giving me the suggestion.

My constraint file is like this

set_property PACKAGE_PIN G12 [get_ports DIFF_CLK_0_125_Mhz_clk_p]

set_property PACKAGE_PIN F12 [get_ports DIFF_CLK_0_125_Mhz_clk_n]


create_clock -period 8 -name i_125MHz_clk [get_ports DIFF_CLK_0_125_Mhz_clk_p]


The reason i did not mentioned about IO Standard is that the user guide of KCU116 tells that for LVDS IO stanadard is not applicable.


Later I bypassed DRC error by using this 

set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
set_property SEVERITY {Warning} [get_drc_checks UCIO-1]

 But after bitstream generation i checked this Vivado SDK but it will not work properly.

Actually it will not provide any clock for the processor to come out of the reset.

I will try your method for putting constraints.

 

You also need to verify that the bank is powered by a VCCO voltage that allows the use of the internal resistor
> Can you tell me more about this?

I tried with 300MHz also but same result.

How can I make use of LVDS clocks and what constraints exactly i need to put to make it work properly.

Thank you

Regards
pavan

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Adventurer
Adventurer
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Registered: ‎03-13-2019

Hello,

 

I checked the schematic and there is internal resistor. I used the LVDS constraint but I got this error in the place design phase

[DRC BIVB-1] Bank IO standard Support: Bank 87 has incompatible IO(s) because: The LVDS I/O standard is not supported for banks of type High Density. Move the following ports or change their properties:
DIFF_CLK_0_125_Mhz_clk_p

What will this error indicate?

Thank you

Regards
pavan

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Registered: ‎06-21-2017

I checked the schematics too.  That resistor is external to the FPGA.  Since this is an HD bank, you cannot use the LVDS IO Standard.  Table 3-2 of the UltraScale Architecture SelectIO Resources (UG571) says you must use the LVDS_25 IO Standard.

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Adventurer
Adventurer
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Registered: ‎03-13-2019

Hello thank you for the suggestion.

I will try this method and update here.

By the way i have one question regarding the input clock

Input pin (125Mhz pin) -> IBUFDS-> BUFG 
is this connection proper or i have to use clock wizard IP from xilinx?

Please suggest me your thought on this.

Thank you

pavan

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Adventurer
Adventurer
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Registered: ‎03-13-2019

Hello,

Finally my system is working with 125MHz clock pin.

My system is like this

Clock pin-> IBUFDS->BUFG->Clock wizard -> clock output to microblaze system (125MHz output)

Constraints are :

set_property PACKAGE_PIN G12 [get_ports DIFF_CLK_0_125_Mhz_clk_p]

set_property IOSTANDARD LVDS_25 [get_ports DIFF_CLK_0_125_Mhz_clk_p]
set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets micro_test_i/util_ds_buf_1/U0/BUFG_O[0]]
-> This constraint was suggested by vivado during build stage.

My design is working (helloworld is printing in teraterm) but my concern is can this constraint will affect anything?

Why i need to use this constraint?
Thank you
Regards
pavan
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