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Contributor
Contributor
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Registered: ‎03-04-2019

How to use Fixed point!

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I'm use vivado 2019.1.2

I checked following directory files  (fixed_float_types_c.vhd, fixed_pkg_c.vhd)

C:\Xilinx\Vivado\2019.1\ids_lite\ISE\vhdl\src\ieee

C:\Xilinx\Vivado\2019.1\ids_lite\ISE\vhdl\src\ieee_proposed

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;

library ieee_proposed;
use ieee_proposed.fixed_pkg.all;

entity FFTA is
         Port ( CLK,RSTN : in STD_LOGIC;
         Fixed_Din : in sfixed(2 downto -13):=X"8120";
        Fixed_Dout : out sfixed(2 downto -13):=(others => '0')

);
end FFTA;

 

architecture Behavioral of FFTA is

begin


PROCESS(CLK,RSTN)
VARIABLE TEMP : SFIXED(2 DOWNTO -13):=X"0008";
BEGIN
   IF RSTN='0' THEN
      Fixed_Dout<=(OTHERS=>'0');
   ELSIF CLK'EVENT AND CLK='1' THEN
      Fixed_Dout<=Fixed_Din + TEMP;
   END IF;
END PROCESS;

end Behavioral;

 

But error!

[IP_Flow 19-734] Port 'Fixed_Din': Port type 'sfixed' is not recognized. Only std_logic and std_logic_vector types are allowed for ports. See the documentation for more details.

[IP_Flow 19-734] Port 'Fixed_Dout': Port type 'sfixed' is not recognized. Only std_logic and std_logic_vector types are allowed for ports. See the documentation for more details.
[IP_Flow 19-734] Port 'Fixed_Din': Port type 'sfixed' is not recognized. Only std_logic and std_logic_vector types are allowed for ports. See the documentation for more details.

 

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1 Solution

Accepted Solutions
512 Views
Registered: ‎03-27-2014

@ghkdkrtks 

the solution is in the error message


@ghkdkrtks wrote:

Only std_logic and std_logic_vector types are allowed for ports


you need to cast fixed_dout to std_logic_vector before connecting to the output port

you need to convert fixed_din from std_logic_vector to 'sfixed' before using it. Online documentation will tell you how to do this

gw.
Embedded Systems, DSP, cyber

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3 Replies
513 Views
Registered: ‎03-27-2014

@ghkdkrtks 

the solution is in the error message


@ghkdkrtks wrote:

Only std_logic and std_logic_vector types are allowed for ports


you need to cast fixed_dout to std_logic_vector before connecting to the output port

you need to convert fixed_din from std_logic_vector to 'sfixed' before using it. Online documentation will tell you how to do this

gw.
Embedded Systems, DSP, cyber

View solution in original post

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Scholar
Scholar
499 Views
Registered: ‎08-01-2012

What are you trying to compile in? In normal RTL synthesis any types can be used on ports.

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Xilinx Employee
Xilinx Employee
483 Views
Registered: ‎06-14-2018

Hi @ghkdkrtks 

Could you please try in latest release.

One more thing is 

  Fixed_Dout<=Fixed_Din + TEMP;

result of above will be 1 bit more than FIxed_Din

you need to have Fixed_Dout of size (3 downto -13) or (2 downto -14)

Thanks,

Ajay

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