I don't understand "Xst:790-Index value(s) does not match array range, simulation mismatch." message.

[gekuls21]

I don't understand the following warning message...

"Xst:790-Index value(s) does not match array range, simulation mismatch."

My coding is as following

------------------------------------------------------------------------------------------

     type stc_scid is array(0 to 19) of std_logic_vector(5 downto 0);
     type stc_sad is array(0 to 19) of std_logic_vector(9 downto 0);
     type stc_tpl is array(0 to 19) of std_logic_vector(5 downto 0);
     type stc_stl is array(0 to 19) of std_logic_vector(9 downto 0);
     signal SCID : stc_scid;
     signal SAD : stc_sad;
     signal TPL : stc_tpl;
     signal STL : stc_stl;

                                                  .

                                                  .

                                                  .

     variable stc_cnt : integer range 0 to 19 :=0;  -- stc_cnt can't have values bigger than 19

                                                  .

                                                  .

                                                  .

                                                  .

      SCID(stc_cnt) <= STC(5 downto 0);

      SAD(stc_cnt) <= STC(9 downto 0);

      TPL(stc_cnt) <= STC(5 downto 0);

      STL(stc_cnt) <= STC(9 downto 0);

--------------------------------------------------------------------------------------------

I think, there is nothing wrong.

I don't understand why the warning message is occured....

Please tells me what is wrong.....

Message Edited by gekuls21 on 04-21-2009 06:12 PM

Message Edited by gekuls21 on 04-22-2009 01:07 AM

[gszakacs]

How did you define "stc_cnt"?  Can it take on values greater than 19?

[gekuls21]

Of cause, I defined stc_cnt  like following

    ---------------------------------------------------------

    variable stc_cnt : integer range 0 to 19 :=0;

    ---------------------------------------------------------

[xilinx_user9]

Take a power of 2 and it will work. (round to a power of two).

0 to 19 can be implemented in real hardware...

[xilinx_user9]

0 to 19 can't... of course...

[ajmirg]

This is due to accessing an array with length less than a power of 2. 

This simulation mismatch message is sometimes not valid. For example, there is an array of 0 to 9 and a counter is used to access the array but the counter logic synthesized is shown to be implemented with a count limit, which is 9. A simulation mismatch message can still be seen despite there won't be simulation mismatch. In this case this message is not valid. I have tested with the new parser XST-2 and this simulation mismatch is not there for the above example given.

If you have hundreds of these warnings, you may want to filter these messages by Edit> Message Filters.

Cheers,

[Anonymous]

Thanks  dear...! It works..

[sirazsk]

I am a noob in vhdl,

I am also getting same type of warning : line 129: Index value(s) does not match array range, simulation mismatch.

--declaration of MAS & MASS SIGNAL

SIGNAL MAS : STD_LOGIC_VECTOR(15 DOWNTO 0);

SIGNAL MASS : STD_LOGIC_VECTOR(3 DOWNTO 0);

                    .

                    .

                    .

                    .

FOR x IN 0 TO 3 LOOP
     MAS(x)<=MA2(x);
END LOOP;
FOR I IN 4 TO 15 LOOP
     MAS(x) <= '0';
END LOOP;

                    .

                    .

                    .

                    .

FOR x IN 0 TO 3 LOOP
      MASS(x)<=MAS(x+DIFI);   --the warning occurs over here 
END LOOP;

Please tell me what is wrong ...

I dont know why the warning came ...