01-11-2019 03:54 PM
So, in my code here, I have two integers whose values are supposed to change every time the input data to the module changes, and they are both required to change, but still need to be constants for the sake of use in slicing an array. I don't understand why int i is not causing issues, and int j is. Please help me see whatever issue there is that is causing the integer to not pass synthesis. I've tried declaring the integer outside of the always block, I've tried declaring it as a register outside of the always block and re-assigning it (without using "assign" of course) in the always block. I just feel stumped!
01-12-2019 04:12 AM
If we look at the code, there is a difference in usage of both the integer. If I understand correctly, both are dependent on inputs. While "i" is used to assign the value to an element of the array, j is used to change the array size at runtime which is not allowed. The range boundation should not change at runtime.
01-12-2019 05:41 AM
How so? The problem statement "o_pl_inst = csh_reg[j:j-127]; " is actually an attempt to assign o_pl_inst with the slice of csh_reg[ ] that starts at index j, and includes the 127 elements below j.
01-13-2019 05:59 AM - edited 01-13-2019 06:01 AM
@danm992 ' "o_pl_inst = csh_reg[j:j-127];" is actually an attempt to assign o_pl_inst with the slice of csh_reg[ ] that starts at index j, and includes the 127 elements below j '
Vivado Synthesis doesn't handle dynamic slicing very well, see:
AR# 52302 Vivado Synthesis - Does Vivado Synthesis support non-constant (dynamic) range expression?
"Vivado Synthesis does not always support variables on both bounds of a range."
I've had to rewrite code, that's worked for decades in other tools, because of this issue.
I've worked around similar problems with Vivado by looping over each bit of the slice individually.
Note also that this bug appears in the Vivado 2012.x list of Synthesis Known Issues:
Given the 2012 date, one can infer the amount of effort being applied to the VHDL/Verilog Synthesis tool needed by the majority of Xilinx's existing FPGA customers.
01-13-2019 06:11 AM
Thanks for letting me know! What would be an alternative?
01-13-2019 07:08 AM
@danm992 "What would be an alternative?"
From my earlier reply : "I've worked around similar problems with Vivado by looping over each bit of the slice individually."
i.e., try looping through the 128 elements individually, with a single-index bit slice on each side of the assignment.
Although after looking at your entire code, if I'm reading it correctly, it appears you're trying to extract 128 bits from a 128 megabit vector- you'll likely have other problems getting this to synthesize...
If you're trying to infer a 1 megaword, 128 bit wide memory, look at the memory inference templates in UG901; but I'd note that 128 megabits is an awfully large size to build up from the 32 kilobit BRAMs available in the typical FPGA.