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srdatucsd
Adventurer
Adventurer
938 Views
Registered: ‎09-06-2016

I wanna believe, but....

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I'm seeing these kinds of complaints a lot.  They do not make sense after doing block refresh and verify design without error.

Vivado_Nonsense_ 2020-10-02.jpg

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florentw
Moderator
Moderator
643 Views
Registered: ‎11-09-2015

Hi @srdatucsd 

Ok. I never used this different views. 

So I am able to reproduce the warning but only if I connect the pin between 2 inputs:

warning.PNG

So it takes sense in this case.

Each time I connect an output port to drive this pin, the warning disappear.

So if you have a test case with the port correctly driver but vivado still producing a warning, please package your project so I can analyze it


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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dgisselq
Scholar
Scholar
885 Views
Registered: ‎05-21-2015

@srdatucsd ,

I can't read your image.  What types of complaints are you talking about?

Dan

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avrumw
Expert
Expert
858 Views
Registered: ‎01-23-2009

I can't read your image

If you click on an image, it appears in a pop-up window in the browser. In this view it is no larger than the original image. However, in the top right corner of the pop-up there is a button to expand the image to full screen. Using this, the image (including the error message) is readable.

avrumw_0-1601754900619.png

Avrum

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florentw
Moderator
Moderator
786 Views
Registered: ‎11-09-2015

HI @srdatucsd 

What version are you using?

Do you have any test case to share (should be easy to reproduce but a test case would be faster)


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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dpaul24
Scholar
Scholar
770 Views
Registered: ‎08-07-2014

@srdatucsd ,

If you do not explain your problem, so we can only make speculations.

This is what I could make out from your screenshot...

3 input ports in your design are unconnected and so Vivado flags a Critical Warning message. Check if they should be this way and correct it. If they are unused, just remove them to proceed with Synth.

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srdatucsd
Adventurer
Adventurer
744 Views
Registered: ‎09-06-2016

I'm using 2019.2

I thought the screenshot to be self-explanatory.  It says things are not connected in the error messages, that are obviously connected - unless the IP diagram is a lie.  The RTL has the proper ports as well.  I do not have a test case and do not know how to create one for a VIvado bug like this.

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florentw
Moderator
Moderator
731 Views
Registered: ‎11-09-2015

HI @srdatucsd 

One thing which is strange is the view of the IP. This is what I have in vivado 2019.2:

reset.PNG

As you can see, all the ports which are supposed to be inputs of the IPs are on the left (including aux_reset_in) and all the port which are outputs are on the right.

Also, even if it stays unconnected, I do not get any warning...

Did you change anything in the settings of vivado which might give this? What OS are you using?

Can you send a test case?

And can you send me the txt file output from report_environment -file Env.txt ?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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srdatucsd
Adventurer
Adventurer
708 Views
Registered: ‎09-06-2016

If you play with the block display options, say to remove loops, it will shuffle inputs and outputs around in ways that 'make sense' to the programmer of the graphical interface.  I have no control over where things end up for clarity as a hardware designer.    Inputs can be on the right and I think outputs can be on the left.  I cannot even control the IP block placement grid.

That is the only thing I knowingly changed other than trying different routing strategies.  I am unable to send a test case.  I have moved on from this problem (critical schedule to meet) as It cured itself after multiple changes and re-imps.  If I can ever find that file you requested, I'll send it, but I think it is gone.  It seems a problem that Xilinx should be interested in solving though, and I will report here if/when it returns.

I am running on Ubuntu 16.04 for 2019.2.

Thanks for taking the anomaly seriously.

 

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florentw
Moderator
Moderator
644 Views
Registered: ‎11-09-2015

Hi @srdatucsd 

Ok. I never used this different views. 

So I am able to reproduce the warning but only if I connect the pin between 2 inputs:

warning.PNG

So it takes sense in this case.

Each time I connect an output port to drive this pin, the warning disappear.

So if you have a test case with the port correctly driver but vivado still producing a warning, please package your project so I can analyze it


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

srdatucsd
Adventurer
Adventurer
613 Views
Registered: ‎09-06-2016

Will do.  Mine is driven for sure.  To be continued on recurrence.

P.S.  I'm finding packaging a project a daunting task, i.e., to generate the TCL that would recreate it.  For example, write_bd_tcl leaves too much to figure out after the fact and the latter is error prone.

But that is a different issue.

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