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Xilinx Employee
Xilinx Employee
346 Views
Registered: ‎07-23-2018

IO buffer insertion invalidates scoped constraints

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Consider that I have an RTL block "submodule.v", and a top level "top.v". It is guaranteed that there will be only one instance of "submodule".

`timescale 1ns / 1ps
module submodule (
    input a,
    input b,
    output reg c,
    input clk,
    input rstn
);
    always @(posedge clk) begin
        if (~rstn) begin
            c <= 1'b0;
        end
        else begin
            c <= a | b;
        end
    end
endmodule
`timescale 1ns / 1ps
module top (
    input a,
    input b,
    output c,
    input clk,
    input rstn
);
    submodule sub_inst (
        .a    (a),
        .b    (b),
        .c    (c),
        .clk  (clk),
        .rstn (rstn)
    );
endmodule

Now I would like to write constraints at the submodule scope, as "top" can be out of my control except for the sole instance of "submodule". So I come up with the follow XDCs, where the pins are arbitrarily chosen just for illustration purpose.

set_property PACKAGE_PIN AM16 [get_ports a]
set_property PACKAGE_PIN AM17 [get_ports b]
set_property PACKAGE_PIN AM18 [get_ports c]
set_property PACKAGE_PIN AM19 [get_ports clk]
set_property PACKAGE_PIN AM20 [get_ports rstn]

The issue is that when I run synthesis, Vivado automatically inserts IO/clock buffers between "top" and "submodule". This prevents the scoped constraints from taking effect, as "get_ports" effectively reduces to "get_pins" and returns "sub_inst/a" instead of the port "a". So the constraints cannot be applied to the design ports. See the synthesized result as follows.

Capture.PNG

I tried to manually instantiate IBUF and OBUF inside "submodule". If I do not set DONT_TOUCH, Vivado removes those instances; otherwise, Vivado throws errors.

This looks exactly the same as the example in UG903 Pg. 70. What is the correct way to let synthesizer move the buffers into submodule?

 

Thanks and regards,

Yan

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Moderator
Moderator
303 Views
Registered: ‎11-04-2010

Re: IO buffer insertion invalidates scoped constraints

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Hi, @yanz ,

For the submodule source code, don't forget to instantiate I/OBUF.

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Moderator
Moderator
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Registered: ‎11-04-2010

Re: IO buffer insertion invalidates scoped constraints

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Hi, @yanz ,

You can try to add the io_buffer_type to none for the top level ports, which you don't need insert I/OBUF.

(* io_buffer_type = “none” *) input in1;

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-23-2018

Re: IO buffer insertion invalidates scoped constraints

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Hi @hongh ,

Thanks for the suggestion. I tried to set io_buffer_type to "none". This did remove the IO buffers. But during implementation, Vivado would complain that all IOs need to be buffered.

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-22-2018

Re: IO buffer insertion invalidates scoped constraints

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Hi @yanz ,

Also you can set -mode out_of_context in more option under synthesis settings, it will disable the buffer indsertion:

Capture.PNG

Thanks,

Raj

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Moderator
Moderator
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Registered: ‎11-04-2010

Re: IO buffer insertion invalidates scoped constraints

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Hi, @yanz ,

For the submodule source code, don't forget to instantiate I/OBUF.

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-23-2018

Re: IO buffer insertion invalidates scoped constraints

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Hi @rshekhaw ,

My goal is not to disable buffer insertion, but to move the buffers inside sub_inst so that the scoped constraints can be applied.

My understanding of out-of-context mode is to treat the module "top" as an IP block. In this case, does it still make sense to do P&R on "top"?

Thanks and regards,

Yan

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-23-2018

Re: IO buffer insertion invalidates scoped constraints

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Hi @hongh 

Looks like there was something wrong with my project environment. With a clean project, I can prevent the auto buffer insertion by instantiating I/OBUF in the submodule accordingly.

Thanks for the help.

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