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Newbie
Newbie
9,000 Views
Registered: ‎12-05-2010

ISE 12 Synthesis Error

Hi,

I'm using ISE 12.2 for a MIG QDR2 project. Top module is a schematic file. When I run synthesis, it fails due to an error in vhf file. The ports of one of my submodule is not visible. Actually submodule passes "check syntax" and I can see the symbol of that module.

 

The error in synthesis is :

 

HDLParsers:164 - "D:/serguven/codes/qdr2_controller/qdr2_controller/qdr2_controller.vhf" Line 295. parse error, unexpected CLOSEPAR, expecting IDENTIFIER sch2hdl -intstyle ise -family virtex5 -flat -suppress -vhdl

 

Do you have any advice? Is there a hierarchy problem in ISE 12?

 

 The submodule is written below :

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity qdr2_read_addr_gen is
    Port ( clk0 : in  STD_LOGIC;
           rst0 : in  STD_LOGIC;
           ena0 : in  STD_LOGIC;
           user_rd_full : in  STD_LOGIC;
           packet_size : in  STD_LOGIC_VECTOR(13 downto 0);
           packet_read_trig : in  STD_LOGIC;
           total_data_size : in  STD_LOGIC_VECTOR(18 downto 0);
           opc : out  STD_LOGIC;
           packet_opc : out  STD_LOGIC;
           user_r_n : out  STD_LOGIC;
           user_ad_rd : out  STD_LOGIC_VECTOR(18 downto 0));
end qdr2_read_addr_gen;

architecture Behavioral of qdr2_read_addr_gen is

type mig_read_addr_states is ( Reset_State, Wait_Packet_Read_Trig_State,  Check_Addr_Fifo_State, NOP_Addr_State, Write_Addr_State, Pause_State);
signal mig_read_addr_state    : mig_read_addr_states;

signal user_ad_rd_s       : STD_LOGIC_VECTOR(18 downto 0);
signal NOP_counter_addr_s  : STD_LOGIC_VECTOR(3 downto 0);
signal total_data_size_s   : STD_LOGIC_VECTOR(18 downto 0);
signal pause_counter    : STD_LOGIC_VECTOR(2 downto 0);
signal packet_size_s    : STD_LOGIC_VECTOR(13 downto 0);
signal packet_data_counter_s  : STD_LOGIC_VECTOR(13 downto 0);

begin

read_data_state_control : process (clk0, rst0)
begin 
    
 if rst0 = '1' then    
   
   user_ad_rd_s <= (others => '0');
   user_r_n <= '1';
   NOP_counter_addr_s <= (others => '0');
   total_data_size_s <= (others => '0');
   pause_counter <= (others => '0');
   packet_data_counter_s <= (others => '0');
   mig_read_addr_state <= Reset_State;
   opc <= '1';
   packet_opc <= '1';
 
   elsif rising_edge(clk0) then
    
    user_ad_rd <= user_ad_rd_s;
    
    case mig_read_addr_state is
     
     -------------------------------------------------------------
     
      when Reset_State =>
      
      packet_opc <= '1';
      
      if ena0 = '1' then
       mig_read_addr_state <= Check_Addr_Fifo_State;--ilk paket otomatik olarak gonderiliyor
       opc <= '0';
       packet_opc <= '0';
       total_data_size_s <= total_data_size;
       packet_size_s <= packet_size;
      end if;
      
      user_ad_rd_s <= (others => '0');
      user_r_n <= '1';
      NOP_counter_addr_s <= (others => '0');
      pause_counter <= (others => '0');
      packet_data_counter_s <= (others => '0');
      

     -------------------------------------------------------------
      
      when Wait_Packet_Read_Trig_State =>
      
      if packet_read_trig = '1' then
       mig_read_addr_state <= Check_Addr_Fifo_State;
       packet_opc <= '0';
      end if;
      
     -------------------------------------------------------------  
              
      when Check_Addr_Fifo_State =>
         
      if(user_rd_full = '1') then
       mig_read_addr_state <= Check_Addr_Fifo_State;
      else
       mig_read_addr_state <= NOP_Addr_State;
      end if;
      
      
     -------------------------------------------------------------
     
       when NOP_Addr_State =>
      
       if (NOP_counter_addr_s = "0011") then
        mig_read_addr_state <= Write_Addr_State;
       NOP_counter_addr_s <= (others => '0');
       else
       mig_read_addr_state <= NOP_Addr_State;
       NOP_counter_addr_s <= NOP_counter_addr_s + 1;
       end if;
    
     -------------------------------------------------------------
     
      when Write_Addr_State => 
      
      if(user_rd_full = '1') then
       mig_read_addr_state <= Check_Addr_Fifo_State;
       user_r_n <= '1';
      else
       if user_ad_rd_s = total_data_size_s then
        user_r_n <= '1';
        mig_read_addr_state <= Reset_State;
        opc <= '1';
        packet_opc <= '1';
       elsif packet_data_counter_s = packet_size_s then
        user_r_n <= '1';
        packet_opc <= '1';
        packet_data_counter_s <= (others => '0');
        mig_read_addr_state <= Wait_Packet_Read_Trig_State;
       else
        mig_read_addr_state <= Pause_State;
        user_ad_rd_s <= user_ad_rd_s + 8;
        packet_data_counter_s <= packet_data_counter_s + 4;
        user_r_n <= '0';
       end if;
      end if;
      
     ------------------------------------------------------------
     
      when Pause_State =>
      
      user_r_n <= '1';
      
      if pause_counter = "011" then
       mig_read_addr_state <= Write_Addr_State;
       pause_counter <= (others => '0');
      else
       pause_counter <= pause_counter + 1;
      end if;
     
     -------------------------------------------------------------
     when others =>
      
       
      mig_read_addr_state <= Reset_State;
     
     -------------------------------------------------------------
    end case;
 end if;
end process;

end Behavioral;

 

 

 

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10 Replies
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Xilinx Employee
Xilinx Employee
8,987 Views
Registered: ‎08-08-2007

Re: ISE 12 Synthesis Error

It appears that the VHDL code that you posted in the the VHDL code referenced in the error message.  Specifcally, the error message points to file qdr2_controller.vhf, line 295.

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Xilinx Employee
Xilinx Employee
8,968 Views
Registered: ‎05-14-2008

Re: ISE 12 Synthesis Error

Seems that the problem is with the top level but not the submodule. Do you get the error if you synthesize only the schematic file of the top level?

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Highlighted
Newbie
Newbie
8,958 Views
Registered: ‎12-05-2010

Re: ISE 12 Synthesis Error

The synthesis in project navigator runs only for the top module. The vhf file of the top module is very diffent from the older versions. In top module, I have only two components, one for dcm, one for memory controller. In memory controller submodule, the related "qdr2_read_addr_gen" file exists. In ISE 12, sch2hdl converter(responsible for vhf generation) converts only the dcm and memory controller(component declaration and port mappings), but in ISE 12, vhf file of the top module includes all of the submodules including the failed one. There seems to be different approach for schmatic to vhdl convertion in ISE 12. I attached the vhf file of the top module.

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Xilinx Employee
Xilinx Employee
8,946 Views
Registered: ‎08-08-2007

Re: ISE 12 Synthesis Error

Looking at the file that you provided, line 295 (and surrounding) has:

 

entity qdr2_read_addr_gen_MUSER_top is
   port ( );
end qdr2_read_addr_gen_MUSER_top;

architecture BEHAVIORAL of qdr2_read_addr_gen_MUSER_top is
begin
end BEHAVIORAL;


An empty entity got created but later down in the VHDL file, there is a component declaration that has everything defined.  Double check your schematic that everything is connected together as it should be.

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Highlighted
Observer
Observer
8,904 Views
Registered: ‎10-01-2010

Re: ISE 12 Synthesis Error

Hello Sir, 

 

i have problem here in my code , realted to for loop...kindly some one have look  on it :mansad:

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Mentor
Mentor
8,901 Views
Registered: ‎11-29-2007

Re: ISE 12 Synthesis Error

  • STOP posting unrelated questions in existing threads. This is confusing and rude.
  • How are we supposed to help you if you don't tell us what your problem is?!

So:

  1. Open a new thread.
  2. Post your question there, and write a detailed, but concise, description of your problem.

 

Adrian



Please google your question before asking it.
If someone answers your question, mark the post with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left).
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Observer
Observer
8,897 Views
Registered: ‎10-01-2010

Re: ISE 12 Synthesis Error

 code is done with simulation , but syenthesis failure ......first i did fix the for loop with variable for(i=0;i<v;i=i+1)

 

but then  its gives the for loop error 

 

          ERROR:Xst:2634        For loop stop condition should depend on loop variable or be static. 

 

so   then i fixed it with for(i=0;i<4;i=i+1) but again the same error ...

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Mentor
Mentor
8,895 Views
Registered: ‎11-29-2007

Re: ISE 12 Synthesis Error

What did I just tell you about opening a new thread? Go to the Synthesis forum and click on "New message".



Please google your question before asking it.
If someone answers your question, mark the post with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left).
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Highlighted
Newbie
Newbie
8,884 Views
Registered: ‎12-05-2010

Re: ISE 12 Synthesis Error

Hello,

 

I checked my connections. Also run design rules and check syntax for every module. There is no problem. I also opened a webcase for this issue. I think, it's related to a hierchical problem in ISE 12. sch2hdl command for vhf generation fails.

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Highlighted
2,317 Views
Registered: ‎05-10-2011

Re: ISE 12 Synthesis Error

Was there a solution to this posted elsewhere?

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