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Adventurer
Adventurer
8,992 Views
Registered: ‎03-31-2014

ISE synthesis error

Hi,

I'm encountering the following error while trying to synthesize the design. CAn anyone help with the resolution.?

 

ConstraintSystem:59 - Constraint <NET "FLASH_SPI_CLK" IOSTANDARD = LVCMOS33;> [TOP.ucf(179)]: NET "FLASH_SPI_CLK" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file.

 

Thanks,

Asan.

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7 Replies
Moderator
Moderator
8,990 Views
Registered: ‎06-24-2015

Re: ISE synthesis error

Hi,

 

Refer to this link:
http://www.xilinx.com/support/answers/34258.html

 

Thanks,
Nupur

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Thanks,
Nupur
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Instructor
Instructor
8,989 Views
Registered: ‎08-14-2007

Re: ISE synthesis error

Actually that's a translation error, not synthesis.  It says you have a constraint that doesn't match any element of the design.  Check your top level design unit to make sure you actually have a port called "FLASH_SPI_CLK" and that it is connected (not trimmed out) to logic in the design after synthesis.  If it has been trimmed, you should see it in the synthesis report.  Note that at least for Verilog the signal names are case sensitive, so a port named "flash_spi_clk" is not the same as "FLASH_SPI_CLK".  You can also open the synthesized design in PlanAhead and look through the IO ports to see if this signal still exists and under what name.

-- Gabor
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Moderator
Moderator
8,966 Views
Registered: ‎07-21-2014

Re: ISE synthesis error

@ajasan

 

Open the technology schematic and see whether the listed net is present or trimmed out by the XST.

 

Thanks,
Anusheel
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Thanks
Anusheel
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Adventurer
Adventurer
8,958 Views
Registered: ‎03-31-2014

Re: ISE synthesis error

Hi All,

Thanks for the response.

 

I have checked in the schematic also. The net is present. and I understand the particular net is not removed by the synthesis process.

 

Could there be any other possible reason?

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Adventurer
Adventurer
8,957 Views
Registered: ‎03-31-2014

Re: ISE synthesis error

Gabor,
Yes. It is a translation error. Sorry, I have posted by mistake.
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Instructor
Instructor
8,944 Views
Registered: ‎08-14-2007

Re: ISE synthesis error

One other suggestion is to comment out this constraint and allow the tools to run through place&route.  Then check the pad report to see if FLASH_SPI_CLK is listed.  Also double-check the spelling (including upper case).  Some mis-spellings are not easy to spot like doubled underscores - e.g. FLASH__SPI__CLK.

-- Gabor
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Moderator
Moderator
8,937 Views
Registered: ‎07-01-2015

Re: ISE synthesis error

Hi @ajasan,

 

Please try the following constraint and let us know if it works.

net "FLASH_SPI_CLK" s=true;

 

Thanks and Regards,
Arpan

Thanks,
Arpan
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