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Anonymous
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Ignoring malformed $readmem task: invalid memory name. Why?

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Using Vivado 2016.3 and SystemVerilog source.

 

I'm trying to test block RAM induction and initialization from file, but apparently Vivado refuses to recognize my initialization.

 

My main module is upgm.sv and I have upgm.data as a data file.

 

Main module (upgm.sv):

 

import microaddr_types::uaddr_t;
import plugh_types::upgm_t;

// uProgram ROM. The block RAM resources on Xilinx chips require
// a clock edge for reads.

module upgm(
	input bit clk,
	input uaddr_t addr,
	output upgm_t data
);

upgm_t upgm [2048];

initial begin
	$readmemb("upgm.data", upgm);
end

always_ff @(negedge clk) begin
	data <= upgm[addr];
end // always_ff

endmodule // upgm

Note that the data type, ugpm_t, is essentially a 33-bit vector: bit[32:0], and the address type, uaddr_t, is bit[10:0] (so 2048 locations).

 

A sample of the 2048 lines in upgm.data:

 

0000_0000_0000_0000_000_00000000000_000
0000_0000_0000_0000_000_00000000000_000
0000_0000_0000_0000_000_00000000000_000

(Yes, this is valid SystemVerilog for binary data. "_" is an ignored separator.)

 

Elaboration works fine. Synthesis results in this warning message:

 

WARNING: [Synth 8-2898] ignoring malformed $readmem task: invalid memory name [F:/plugh1/ram_test/ram_test.srcs/sources_1/imports/plugh1/upgm.sv:16]

 

I'm assuming that "memory name" here means file path. I'm pretty sure "upgm.data" is valid, since here are all the sources in ram_test.srcs/sources_1/imports/plugh1:

 

alu_types.sv

microaddr_types.sv

plugh_types.sv

register_types.sv

upgm.data         <---- it's right there!

upgm.sv

 

So, what is Vivado complaining about, and how can I fix it?

 

I've included the project archive in case anyone actually wants to try this and validate their fix.

 

Thanks!

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Anonymous
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Re: Ignoring malformed $readmem task: invalid memory name. Why?

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OK, after trying random things and simplifying the code, I determined a few things:

 

1. That cryptic error message has nothing to do with invalid memory names. It means that Vivado has not recognized the code as being a block RAM, and instead created a huge multiplexer. Which can't be initialized with data (which is presumably what the "memory name" refers to).

 

2. Vivado was unable to recognize that, in the context of memory, a struct is a vector of bits! Replacing upgm_t with bit[$bits(upgm_t)-1:0] allowed Vivado to deduce that block RAM was wanted. I think this is a bug in Vivado. There should be no reason that Vivado can't figure out that a struct is a vector of bits.

 

3. I also found that you really do need a clock in order for Vivado to recognize the code as block RAM. Xilinx chips do not have asynchronous RAM.

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Highlighted
Anonymous
Not applicable
8,166 Views

Re: Ignoring malformed $readmem task: invalid memory name. Why?

Jump to solution

OK, after trying random things and simplifying the code, I determined a few things:

 

1. That cryptic error message has nothing to do with invalid memory names. It means that Vivado has not recognized the code as being a block RAM, and instead created a huge multiplexer. Which can't be initialized with data (which is presumably what the "memory name" refers to).

 

2. Vivado was unable to recognize that, in the context of memory, a struct is a vector of bits! Replacing upgm_t with bit[$bits(upgm_t)-1:0] allowed Vivado to deduce that block RAM was wanted. I think this is a bug in Vivado. There should be no reason that Vivado can't figure out that a struct is a vector of bits.

 

3. I also found that you really do need a clock in order for Vivado to recognize the code as block RAM. Xilinx chips do not have asynchronous RAM.

View solution in original post

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