UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor am17an
Visitor
546 Views
Registered: ‎03-12-2018

Implementing a big synthesisable ram

Jump to solution

Hi I'm using XCKU035, which has 36kb, 18kb primitives for BRAMs. I'm trying to implement an array of size 400kb. What is the best way to achieve this? If I just specify the 400kb size, the synthesis tools chokes. The other choices I see are implementing 18kb rams in a 2d array and using those. 

 

Please help. 

 

Thanks

 

 

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Scholar u4223374
Scholar
754 Views
Registered: ‎04-26-2015

Re: Implementing a big synthesisable ram

Jump to solution

That's odd, the synthesis tool should have no trouble handling 400Kb (or 400KB, for that matter). I've used RAMs that big before.

 

My guess would be that you've got an access pattern that isn't compatible with block RAM - trying to set the address and get the data in one cycle (BRAM requires a clock edge), trying to read/write more than two elements per cycle, etc. In that case the synthesis tool will go back to implementing it as registers, and a mux to access >100K registers will definitely cause it to choke.

2 Replies
Highlighted
Scholar u4223374
Scholar
755 Views
Registered: ‎04-26-2015

Re: Implementing a big synthesisable ram

Jump to solution

That's odd, the synthesis tool should have no trouble handling 400Kb (or 400KB, for that matter). I've used RAMs that big before.

 

My guess would be that you've got an access pattern that isn't compatible with block RAM - trying to set the address and get the data in one cycle (BRAM requires a clock edge), trying to read/write more than two elements per cycle, etc. In that case the synthesis tool will go back to implementing it as registers, and a mux to access >100K registers will definitely cause it to choke.

Visitor am17an
Visitor
482 Views
Registered: ‎03-12-2018

Re: Implementing a big synthesisable ram

Jump to solution

Yup, that was the problem. 

0 Kudos