02-10-2017 05:00 AM
I am confused with the design planning, design wrapper creation, etc.
I want to import the I/O Port configuration from another project and have the changes reflected in the design wrapper. But:
- to be able import I/O ports settings there Synthesis must be performed...
- if I want to perform synthesis the design_wrapper has to be generated
- with the wrapper (VHDL in my case) Vivado creates STRUCTURE architecture and also the READ-ONLY design_1. vhd
- If I add the ports manually into the wrapper file then there is later an error that formal port is not defined in design_1.vhd but I am not able to add the ports to design_1.vhd because it is read-only :-(
- if the Synthesis is run and synthesized design opened then it is possible to import I/O configuration but...
- imported I/O configuration is reflected nowhere - the design_1_vhd, design_1_wrapper.vhd are the same as before importing...
What I am missing, please?
I want to be able to create the Block design, import the I/O Pins configuration }and if possible also all other settings, create wrapper and constraints file reflecting the imported I/O settings (name of ports, etc.)
Also, is it possible to let Vivado generate other architectures than STRUCTURE, i.g. behavioral to be able to add processes and user code? Or is there another approach?
Sorry for the maybe easy question - I am a beginner in Vivado and VHDL...
Thank you for any advices...
02-13-2017 02:25 AM
Hello to everyone,
so OK, if there is nobody who knows the answer to my questions I have the easier one (at least I hope that it is really easier :-)):
How can I edit the project/design GPIO ports (names, directions, etc.) still BEFORE the design wrapper generation so that these properties are reflected by the design wrapper generator? If the ports are manually written inside the editable (copied) design_1_wrapper.vhd file then the error occurs saying that there are not corresponding formal ports defined in the design_1.vhd file so I need to make the ports changes before these 2 files (design_1.vhd, design_1 _wrapper.vhd) are created.
I have the same design in Verilog where the ports are already defined with the names LED, IIC_CLK, IIC_SDA, etc. The wanted port names and directions are present in the design_1 _wrapper. I need to convert the project to VHDL. If I configure the Zynq_processing_system by the .tcl exported from the Verilog project (Presets Export, Import), everything looks like to be configured well but the names in generated VHDL wrapper are not the same...
Am I missing something?
Thank you for any idea/comment.