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Contributor
Contributor
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Registered: ‎05-22-2018

Inferring DSP with no pipeline.

Hi,

I want to tell Vivado synthesizer to infer DSP with no pipelining in it. I do not want sequential DSP elements.
I am using Ultrascale (xcvu440) FPGA.

I have been given an RTL code and I cannot change the code. I just want to tell Vivado that while synthesizing, it should not put pipelines in the DSP elements.

How can I do this?

Thanks.

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1 Reply
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265 Views
Registered: ‎01-22-2015

Re: Inferring DSP with no pipeline.

@shantan1 

Below you will find example-VHDL that infers use of the DSP48 for the multiplication, P = A * B, shown in VHDL process, PR1.  None of the pipeline registers found in the DSP48 will be enabled.

In process, PR2, you will see that I have used P2, A2, and B2 to pipeline P, A, and B outside the DSP48.  With this external pipelining, the DONT_TOUCH attribute on P, A, and B is necessary to prevent the DSP48 from automatically pipelining itself by pulling-in the registers associated with P, A, and B.  

    constant NBIT : integer := 16;
    signal A,B,A2,B2 : unsigned((NBIT-1) downto 0);
    signal P,P2 : unsigned((2*NBIT-1) downto 0);
    --
    attribute DONT_TOUCH : string;
    attribute DONT_TOUCH of P,A,B : signal is "TRUE";
    attribute USE_DSP : string;
    attribute USE_DSP of P : signal is "YES";
    --
    PR1: process(clk1)
    begin
        if rising_edge(clk1) then
            P <= A * B;
        end if;
    end process PR1;
    --
    PR2: process(clk1)
    begin
        if rising_edge(clk1) then
            P2 <= P;
            A <= A2;
            B <= B2;
        end if;
    end process PR2;

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