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Teacher
Teacher
1,008 Views
Registered: ‎06-16-2013

Inhibit merged flip flop procesure in a specific module by Vivado

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Hi expart

I'd like to inhibit merged flip flop procesure in a specific module during synthesis process by Vivado.
How do I describe it on RTL file or tcl command or XDC file ?

Best regards

 

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Teacher
Teacher
1,336 Views
Registered: ‎06-16-2013

Hi @jmcclusk

 

Thank you for your reply.

I understood your explanation.

After that I found the following ARs. I will refer them.

 

AR #54699

https://www.xilinx.com/support/answers/54699.html

AR #55251

https://www.xilinx.com/support/answers/55251.html

 

Best regards,

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Mentor
Mentor
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Registered: ‎02-24-2014

Add the KEEP attribute to the net that is the output of the registers that should not be merged.   With the advent of physical synthesis, there really shouldn't be a reason to add this attribute, unless they are mapped to output tri-state enable locations (I've seen this go bad in the past).    If you want to prevent merging in a specific instance of a module that occurs multiple times, then you have to use a parameter or a generic to set a flag in the module to signal that the attribute should be used.   This is more difficult in Verilog than VHDL, because attributes in Verilog are still done as pragmas, so they'll have to be wrapped in conditional generate blocks.

 

And of course, you can also add the KEEP attribute as a set_property TCL command in an XDC file.   That also works.

Don't forget to close a thread when possible by accepting a post as a solution.
Highlighted
Teacher
Teacher
1,337 Views
Registered: ‎06-16-2013

Hi @jmcclusk

 

Thank you for your reply.

I understood your explanation.

After that I found the following ARs. I will refer them.

 

AR #54699

https://www.xilinx.com/support/answers/54699.html

AR #55251

https://www.xilinx.com/support/answers/55251.html

 

Best regards,

View solution in original post

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