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AR
Visitor
Visitor
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Registered: ‎04-08-2021

Initialising BRAM using $readmemb?

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Hi, I'm trying to make vivado infer BRAM to store data from two external data files, I've tried using ram_style, I tried using the language template and I've read nearly all the AR's regarding readmemb/h. I feel like I'm missing something obvious or maybe this isnt possible? Thanks in advance! P.s. using verilog and vivado 2020.1

 

 

(* ram_style = "block" *) reg [7:0] imageArray [0:783];
(* ram_style = "block" *) reg [7:0] patternArray [0:63];

initial
begin
$readmemb("284in1.mif",imageArray, 0,783); 
end
initial
begin
$readmemb("pattern.mif",patternArray, 0, 63); 
end

 

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varunra
Xilinx Employee
Xilinx Employee
454 Views
Registered: ‎01-24-2017

Hi @AR 

I have gone through the code. all the RAMS are read asyncly, so vivado will infer distributed ram.

View solution in original post

12 Replies
varunra
Xilinx Employee
Xilinx Employee
748 Views
Registered: ‎01-24-2017

Hi,

I tried the above of usage, i didn't see any issue with vivado 2020.1 , it inferred 2-BRAM. and read the mif files successfully. can you clearly mention the issue you are facing?

or paste the complete code so that we can debug?

**Just make sure that you are using SYNCHRONOUS read. if not vivado will infer distributed ram

 

Regards

Varun Raj 

viviany
Xilinx Employee
Xilinx Employee
737 Views
Registered: ‎05-14-2008

Below is from UG901. To infer a BRAM as a ROM (storing data in BRAM), you also need the coding in red rectangle to describe the BRAM read/write behavior.

initial_readmemb.png

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AR
Visitor
Visitor
708 Views
Registered: ‎04-08-2021

Thanks for the reply, I'm not sure how to check if i am using sync read? The problem I am having is that LUTRAM/LUT is being inferred but I'm over utilized in these areas, if i can get the data to be stored in BRAM it would save some room for me.

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AR
Visitor
Visitor
707 Views
Registered: ‎04-08-2021

I'm trying to infer the ram in the top module of my design, the entire module >1000 lines is based on the data being read into the top module, i would have to rewrite a lot of code to make a separate module I think, Thanks.

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varunra
Xilinx Employee
Xilinx Employee
623 Views
Registered: ‎01-24-2017

Hi,

Can check if reading data from ram, is it under clock? if not move it to always @(posedgeclock). that should work

Thanks

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AR
Visitor
Visitor
592 Views
Registered: ‎04-08-2021

Hi,

Tried that and still the same result! is there a min size the data needs to be for bram? Currently at 22*784 so 17248 bits. Ive seen 18k and 36k so do i need to make my array a bit bigger?

Thanks

 

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varunra
Xilinx Employee
Xilinx Employee
579 Views
Registered: ‎01-24-2017

Hi, it possible to share the code?

 

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AR
Visitor
Visitor
575 Views
Registered: ‎04-08-2021

I'm using the code in the link below, I've altered sizes etc. but no major changes, CNN.v is where I'm having the issue. https://github.com/AniketBadhan/Convolutional-Neural-Network

 

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AR
Visitor
Visitor
567 Views
Registered: ‎04-08-2021

This is the all I have changed at the beginning.

`timescale 1ns / 1ps

`define IMAGEROW	28
`define IMAGECOL	28
`define PATTERNROW	8
`define PATTERNCOL	8
`define FILTERROW	3
`define FILTERCOL	3
`define CONVROW		26
`define CONVCOL		26
`define MAXROW 		21
`define MAXCOL		21

(*use_dsp48="yes"*)module CNN (//(*use_dsp48="yes"*)
	input clk,
	input rst,
	output reg [3:0] numberOfTimes_PatterDetected
);

	(*ram_style="{ block}"*)reg [7:0] imageArray [0:783];     //imageximage									//memory buffer for storing image and the convolution of it with the laplacian filter
	(*ram_style="{ block}"*)reg [7:0] patternArray [0:63];	   //patternxpattern								//memory buffer for storing pattern and the convolution of it with the laplacian filter
	(*ram_style="{ block}"*)reg [21:0] stage2Output [0:783];  //imageximage
	(*ram_style="{ block}"*)reg [21:0] stage3Output [0:195];   //1/4 imageximage
always @(posedge clk) begin  
 $readmemb("284in1.mif",imageArray, 0,783);	//899	//16383	//reading image
end
always @(posedge clk) begin 
 $readmemb("pattern.mif",patternArray, 0, 63);    //patternxpattern
end

 

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varunra
Xilinx Employee
Xilinx Employee
455 Views
Registered: ‎01-24-2017

Hi @AR 

I have gone through the code. all the RAMS are read asyncly, so vivado will infer distributed ram.

View solution in original post

AR
Visitor
Visitor
431 Views
Registered: ‎04-08-2021

Thanks for taking the time I appreciate it!

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maheng
Observer
Observer
40 Views
Registered: ‎04-01-2021

请问这个问题最后怎么解决的?

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