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ShubhamA
Visitor
Visitor
293 Views
Registered: ‎05-31-2021

Input <> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

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Hi All.

I am working on a decoder/control unit for my RISC V processor. I am getting the following error when I try to implement it.

WARNING:HDLCompiler:1499 - "F:\Xilinx Codes\RISC_V\Control_Logic.v" Line 21: Empty module <Control_Logic> remains a black box.
WARNING:Xst:647 - Input <Inst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <branch> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 

Here's my code:

//START OF CODE

module Control_Logic(Inst,AluFunc,WERF,BSEL,WDSEL,MWR,PCSEL,branch);

input [31:0] Inst;
input branch;

output reg WERF,MWR;
output reg [1:0] WDSEL,BSEL;
output reg [2:0] PCSEL;
output reg [3:0] AluFunc;

always@(Inst,branch)
begin
if (Inst[6:0]=="0X10011")begin//Writing Back to a Register(R type and I type)
WERF<=1;
AluFunc<={Inst[30],Inst[4:2]};
MWR<=0;
WDSEL<=1;
BSEL<=0;
PCSEL<=0;
end

if (Inst[6:0] == "0010011")begin//Enabling Sign Extension on Immediate values(I type)
BSEL<=1;
MWR<=0;
AluFunc<={Inst[30],Inst[4:2]};
WDSEL<=1;
WERF<=1;
PCSEL<=0;
end

if (Inst[6:0] == "0000011") begin//Load Word
MWR<=0;
WDSEL<=2;
//////////////////////////////
AluFunc<="0000";
//////////////////////////////
WERF<=1;
BSEL<=1;
PCSEL<=0;
end

if (Inst[6:0] == "0100011") begin//Store Word
MWR<=1;
WDSEL<=2;
//////////////////////////////
AluFunc<="0000";
//////////////////////////////
WERF<=0;
BSEL<=2;
PCSEL<=0;
end

if (Inst[6:0] == "1100011") begin//Branch Instructions
MWR<=0;
WDSEL<=1;
WERF<=0;
BSEL<=0;
AluFunc<={Inst[30],Inst[4:2]};
if(branch==1)
PCSEL<=1;
else
PCSEL<=0;
end

if (Inst[6:0] == "1100111") begin//Jump and Link Register
MWR<=0;
WDSEL<=0;
WERF<=1;
BSEL<=1;
AluFunc<="0000";
PCSEL<=2;
end

end

endmodule

//END OF CODE

 

Can you guys please help me out by pointing out why this might be happening, what can I do to fix this and how can this be prevented in further designs?

 

Thank you

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1 Solution

Accepted Solutions
aher
Xilinx Employee
Xilinx Employee
245 Views
Registered: ‎07-21-2014

Hi @ShubhamA,

 

In if conditional expression, you are compairing 7 bit value with string literal due to which condition is never true.

You should instead use number with base specifier as constant in every if condition. for eg-

(Inst[6:0] == 7'b0100011) 

 

-Shreyas

 

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1 Reply
aher
Xilinx Employee
Xilinx Employee
246 Views
Registered: ‎07-21-2014

Hi @ShubhamA,

 

In if conditional expression, you are compairing 7 bit value with string literal due to which condition is never true.

You should instead use number with base specifier as constant in every if condition. for eg-

(Inst[6:0] == 7'b0100011) 

 

-Shreyas

 

----------------------------------------------------------------------------------------------
Try to search answer for your issue in forums or xilinx user guides before you post a new thread.

Kindly note- Please mark the Answer as "Accept as solution" if information provided solves your query.
Give Kudos (star provided in right) to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

View solution in original post