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Observer
Observer
403 Views
Registered: ‎08-08-2018

Is there any way to calculate port width with clogb2

Hello!

I would like to use the following ceiling function to calculate the port witdh of a module interface for a given parameter.

 

////////////////////////////////////////////////////////////////////////////
// function called clogb2 that returns an integer which has the
// value of the ceiling of the log base 2.
// taken from axi interface template
// $clogb2 function only available in system verilog
function integer clogb2 (input integer bd);
    integer bit_depth;
    begin
        bit_depth = bd;
        for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
            bit_depth = bit_depth >> 1;
    end
endfunction

 

 

A minimal example would look like this:

module masc_clogb2 
#(
	parameter my_depth=3
	,parameter my_width=clogb2(my_depth)
)
(
  input  wire                 clk,
  input  wire [my_width-1:0]  input_in,
  output reg  [my_width-1:0]  result_out
);

// do something with input and generate output
always @(posedge clk)
begin
	result_out <= input_in;
end
endmodule

or

module masc_clogb2 
#(
	parameter my_depth=3
)
(
  input  wire                         clk,
  input  wire [clogb2(my_depth)-1:0]  input_in,
  output reg  [clogb2(my_depth)-1:0]  result_out
);

// do something with input and generate output
always @(posedge clk)
begin
	result_out <= input_in;
end
endmodule

Error message: [IP_Flow 19-627] Port 'input_in': XPath expression failed: Unsupported function call or array usage "clogb2" found in expression "(clogb2(spirit:decode(id('MODELPARAM_VALUE.my_depth'))) - 1)".

I donno how to do that. Where to place the clogb2 function? Placing it outside of the module seems to be a problem. But placing it right below the port definition is also not working.

Ans yes, i've read, that system verilog has $clogb2 but I'm using plain verilog.

I tried quite a lot. But it seems I'm missing something.

Is there any way to calculate a port bit width with a module parameter?

Any hint is welcome. Many thanks for your attention!

 

LLAP, Marc.

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7 Replies
Highlighted
Xilinx Employee
Xilinx Employee
384 Views
Registered: ‎06-14-2018

Re: Is there any way to calculate port width with clogb2

Hi @m.schappeit ,

You code is working fine with Vivado version 2019.2.

Parameter my_depth bound to: 3 - type: integer
Parameter my_width bound to: 2 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'masc_clogb2' (1#1)

From Error it looks like you are using IP flow and packaging your own IP.

You can look for

- Do you have another clogb2 function defined elsewhere with different functionality

- What values are expecting as input to function and how are those passed. Look out for other warnings flagged.

 

Thanks,

Ajay

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Scholar
Scholar
356 Views
Registered: ‎09-16-2009

Re: Is there any way to calculate port width with clogb2

@m.schappeit 

Constant functions are allowed to be used within the module header, but defined within the module itself.  This has been the case since Verilog-2001 (and probably -95?)

i.e.

module masc_clogb2 
#(
	parameter my_depth=3
)
(
  input  wire                         clk,
  input  wire [clogb2(my_depth)-1:0]  input_in,
  output reg  [clogb2(my_depth)-1:0]  result_out
);
`include "clogb2.v"

// do something with input and generate output
always @(posedge clk)
begin
	result_out <= input_in;
end
endmodule

Should work fine.

Regards,

Mark

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Highlighted
Observer
Observer
271 Views
Registered: ‎08-08-2018

Re: Is there any way to calculate port width with clogb2

Thank you Ajay and Mark for your fast reply.
This are my current findings / comments:

- I'm not packaging any IP. I'm using a block design that uses verilog modules. (is ip packager invoked in the background?)
- It seems that my example works both in 2019.2 and 2018.3 (dunno what went wrong last time). But:
- Using same code from my example in one of my bigger projects (2018.3) still does NOT work!

- I can't find any other warnings related to this.
- to prevent naming confusion, I renamed the function to my_clogb2
- error msg:
[IP_Flow 19-627] Port 'roi_past_tap_in': XPath expression failed: Unsupported function call or array usage "my_clogb2" found in expression "(my_clogb2(spirit:decode(id('MODELPARAM_VALUE.my_depth'))) - 1)".

The line that causes this:

input wire [my_clogb2(my_depth)-1:0] roi_past_tap_in,


Actually i dunno where to look now, since example project is working.

Any ideas what could went wrong?

Thanks in advance!

LLAP, Marc.

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Highlighted
Xilinx Employee
Xilinx Employee
247 Views
Registered: ‎06-14-2018

Re: Is there any way to calculate port width with clogb2

Hi @m.schappeit ,

Thanks for confirming and trying out with changed name.

As its still failing, this looks like issue, is it possible for you to share testcase.

For workaround, longshot, could you try using `define instead of parameter for my_depth.

//

`define my_depth 3

function integer clogb2 (input integer bd);
integer bit_depth;
begin
bit_depth = bd;
for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
bit_depth = bit_depth >> 1;
end
endfunction

module masc_clogb2
#(
parameter my_width=clogb2(`my_depth)
)
(
input wire clk,
input wire [my_width-1:0] input_in,
output reg [my_width-1:0] result_out
);

// do something with input and generate output
always @(posedge clk)
begin
result_out <= input_in;
end
endmodule

//

Thanks,

Ajay

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Highlighted
Observer
Observer
207 Views
Registered: ‎08-08-2018

Re: Is there any way to calculate port width with clogb2

Hello @apetley,

thanks again for replying.

- I tried round about 1000 variants of this. None is working in my main project but in this minimum examples. Error message:

 [IP_Flow 19-627] HDL Parameter 'my_width (My Width)': XPath expression failed: Unsupported function call or array usage "my_clogb2" found in expression "my_clogb2(3)".

- I even took the big module of my main project and sythesized this one with a minimum example project. This also works fine.

- I deduce from this the problem is within my main project. Unfortunately i cannot provide this a testcase.

I already spend too much time for this and will leave this unresolved for me. Vivado does not provide any further usefull hints for me to digg deeper.

Thanks again for the help.

LLAP, Marc.

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Highlighted
Observer
Observer
203 Views
Registered: ‎08-08-2018

Re: Is there any way to calculate port width with clogb2

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Highlighted
Xilinx Employee
Xilinx Employee
174 Views
Registered: ‎06-14-2018

Re: Is there any way to calculate port width with clogb2

Hi @m.schappeit ,

Thanks for trying out.

Its difficult to root-cause without testcase, and I understand debugging is cumbersome for you too.

As the error suggests its related to IP packager. Though you have confirmed you are not using IP packaging flow.

Could you check in your complete project if you have any packaged IP and if warning issued because of that.

Thanks,

Ajay  

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