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Visitor
Visitor
771 Views
Registered: ‎07-03-2017

Keeping port name same after synthesis.

 
  After synthesis i write out the verilog netlist "FILE->export->netlist". Vivado inserting  an escape character(\) on top module entity.I like to keep the same name on top level entity after synthesis without inserting any character. (Vivado 17.4)


Netlist.v

==========
  input [15:0]\reg_wr_arr[1023] ;
  input [15:0]\reg_wr_arr[1022] ;
  input [15:0]\reg_wr_arr[1021] ;
  input [15:0]\reg_wr_arr[1020] ;
  input [15:0]\reg_wr_arr[1019] ;
  input [15:0]\reg_wr_arr[1018] ;
  input [15:0]\reg_wr_arr[1017] ;

  I already tried these option ,but nothing works.

              1. flatten_hierarchy = none
                 directive          = Default
        
           
             2. Keep_hierarchy @ module level (in RTL)

             3. Don't touch constraint in .xdc
          
             4. @ Entity :
                attribute dont_touch : string;
                attribute dont_touch of tx_top : entity is "true|yes";

Is there anywhy to keep the port name same for top level entity after synthesis as well as P&R.?

 

Thanks,

-GR

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Highlighted
Mentor
Mentor
725 Views
Registered: ‎02-24-2014

It might be simpler to  edit the file and do a global replace of the "\" character with " ".

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