11-25-2020 11:08 PM
In the design LUT is present in the clock path even if the gated_clock_conversion is allowed in the synthesis option and gated_clock = yes in the RTL still the LUT is present on the clock path
11-27-2020 11:09 AM
12-01-2020 11:49 AM
What exactly is the functionality of that LUT? If it is something like an AND gate, this looks like it would be some type of bug that should be fixed. The synthesis tool should figure out any type of unary function and be able to ungate the clocks. Are there any KEEP/DONT_TOUCH/KEEP_HIERARCHY attributes in the design that would prevent the clock conversion from happening?
Also, I agree with the previous post. Instantiating your own clock tree is always a great way to make sure you get the exact clock tree that you want.