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Newbie
Newbie
612 Views
Registered: ‎01-29-2018

Latch problem in a simple CPU project

Hey everyone!

 

I need quick help for my project of a simple CPU unit. It generates latches for all registers and i can't figure it out. I generated the scheme and the permit signals are connected only for 3 registers while in the code i connected every register in the same way

 

Here's a pic of that part of the code: https://imgur.com/a/7DxdM

 

As you can see registers 1 2 3 are done in the same way a as register 4 (also others), but they are the only 3 that work. I generated a schematic and it shows only those 3 are connected from the CU - oWE to the permit signal of those 3 registers - iWE

 

There's a zip also with the project if someone is willing to take a quick look :)

 

 

 

 

 

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Scholar
Scholar
599 Views
Registered: ‎08-01-2012

In the CU.vhd file, you didnt assign the outputs in the IDLE state. This will created latches for all of the select lines.