10-15-2020 05:28 AM
I'm implementing a single logic function (with-select-when statement) in a VHDL file with 19 bits input and 10 bits output. The file has ~164K lines (cases). When I try to synthesize the file, Vivado reports an error saying that the output's target is 10 bits and the source is 11 bits. If I change the output's length to 9 bits (which is wrong, because it is actually 10 bits), Vivado reports that the target is 9 bits and the source is 10 bits (which is a correct error message).
If I try a similar file, which has 6 bits output, it synthesizes fine! Any idea as to what is happening? I've tried this with 2019 and 2020 version and I recreated the project in case that was the problem, but still the same error.
PS: I'm having problems posting code. For some reason whenever I post code, the post gets rejected and disappears from the board...
10-15-2020 06:46 AM
10-15-2020 05:29 AM - edited 10-15-2020 05:29 AM
The files are of the form:
entity test is Generic ( A : natural := 3; B : natural := 16; C : natural := 5; D : natural := 2 ); Port ( address : in STD_LOGIC_VECTOR (A+B-1 downto 0); output : out STD_LOGIC_VECTOR (C*D-1 downto 0)); end test; architecture Behavioral of test is begin with address select output <= "0100110000" when "0000000000000000001", "0101111001" when "0000000000000000010", . . . "1111000010" when "1001111111111111111", "----------" when others; end Behavioral;
10-15-2020 06:46 AM
10-15-2020 07:39 AM - edited 10-15-2020 07:40 AM
@drjohnsmith The file is (obviously) automatically generated from a script. That script generates both files (output width 6 & output width 10). Since the former synthesizes just fine, I do not think there is a typing error in the latter.
Also, I am mapping a logic function. I do not want - for now - to map into BRAMs, because I want to know the LUTs required for each function.
10-15-2020 11:37 AM
10-16-2020 12:53 AM
You were indeed right! The error was caused by a single case, where the output was 11 bits and not 10. This was due to an overflow in the generator script. Despite me explicitly requesting n bits, the python function returned the maximum number of bits between n and the minimum length of the word. I had to scroll through every line in the file to detect the anomaly (wish Vivado would report the specific line as well).
Just a quick note on the file format, to make it easier to read,
Try coding the "0100110000" as B"01_0011_0000"
Thanks, that is a very nice trick! I didn't know that...
Can I ask why you do not want to put the output into a Ram ? Id be surprised if the system does not put it into RAM,
I am running some experiments and I want to measure who many LUTs these logic functions will take up. Whether, in the final design, these functions will be mapped onto BRAM or logic will depend on what resources the rest of the design will require. As a side note, if you need high throughput from these functions, you may be bound to use logic.
Thanks again for the help and the very interesting suggestions @drjohnsmith !