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273 Views
Registered: ‎10-30-2019

Logic getting trimmed

Hi,

I am trying to migrate design from Vivado 2018.2 version to 2019.2 version. I have upgraded all Xilinx IP's in the design instead of re-configuring and regenerating it.

In the synthesis netlist, I see that 90% of the logic is getting trimmed in comparison to the 2018.2 version.

The only change in design is the up-gradation of IP's.

What could be the possible cause of this?

Regards,

Saket

 

 

 

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Xilinx Employee
Xilinx Employee
266 Views
Registered: ‎05-14-2008

Re: Logic getting trimmed

How did you know 90% logic was getting trimmed? By looking at the Synthesis utilization report?

Where did you check the Utilization report?

This AR may be helpful for your question:

https://www.xilinx.com/support/answers/59282.html

-vivian

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263 Views
Registered: ‎10-30-2019

Re: Logic getting trimmed

I checked the --- Report Instances Area Table in the runme.log of the synthesis.

Regards,

Saket

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-14-2008

Re: Logic getting trimmed

And compared with the same part in synthesis runme.log of 2018.3?

-vivian

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Registered: ‎10-30-2019

Re: Logic getting trimmed

Hi @viviany 

Yes Compared the same with 2018.2 version.

Regards,
Saket

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-14-2008

Re: Logic getting trimmed

Can you provide the two Synthesis log files?

-vivian

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