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blowe
Visitor
Visitor
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Registered: ‎12-03-2019

Long running synthesis using Vivado 2018.3 or 2019.2

Hello,

I have a large design that I have successfully converted from Altera to Xilinx. Unfortunately, the design which completes easily in Altera cannot synthesize in Xilinx Vivado. After "Start Cross Boundary and Area Optimization" it keeps running (using up large RAM resources) and ever seems to move past that phase. I have spent a month trying to figure this out and I have narrowed the problem down to the use of large 2 dimensional registers. The logic isnt all that complicated so I am assuming I cannot be the only one with this problem but I havent been able to see any discussions on xilinx forum regarding long running synthesis caused by a large number of 2 dimension registers

So the example below will cause Vivado to hang after "Start Cross Boundary and Area Optimizations" and the "Report RTL Partitions" show rather large instances for the module containing this example code.

For example a module that has these 2D registers. Where ITERATIONS is say 256. I am using a UltraScale+ 13P FPGA and default vivado synthesis settings.

reg [135:0] rUpGradient[ITERATIONS-1:0];
reg [135:0] rDownGradient[ITERATIONS-1:0];

reg [63:0] rResults[ITERATIONS-1:0];

and this pseudo code.

always @ (posedge Clk)
begin
   if (Reset) begin
       rNackError <= 0;
       rProcessError <= 0;
       for (index = 0; index < ITERATIONS; index = index + 1) begin 
           rUpGradient[index] <= 0;
           rDownGradient[index] <= 0;
           rResults[index] <= 0;
           rDifference[index] <= 0;  
       end
   end
   else begin
       rNackError <= 0;
       rProcessError <= 0;
       // new movements dectected
       if (rUpDxn) begin
           rDifference[rIndex] <= 0;
           if (rUpDownDxn) begin
                rResults[rIndex] <= (rDownMovement + rVelocity);
                 rUpGradient[rIndex] <= {rVelocity, rTokenId, rClientId, 8'h1};
           end
       else begin
           rResults[rIndex] <= (rVolatity + rVelocity);
           rDownGradient[rIndex] <= {rVelocity, rTokenId, rClientId, 8'h1};
      end
   end

   // new movements accepted.
   if (rDownDirection) begin
       if (rUpDownDxn) begin  
            rUpGradient[rIndex] <= {rVolatity, rIndexCache, rNeighborCache,
            rFlagsCache[7:2], 1'b1,rFlagsCache[0]};
      end
      else begin
           rDownGradient[rIndex] <= {rDownMovement, rIndexCache, rNeighborCache,
           rDownFlags[7:2], 1'b1,rDownFlags[0]};
      end 
   end

   // collisions of particlies
   if (rCollisionsEna) begin
      if (rUpDownDxn) begin
          rDifference[rIndex] <= ComputeDiffs(rVolatity, rDifference[rIndex]);
          rUpGradient[rIndex] <= {rVolatity,rIndexCache,rNeighborCache,
         rFlagsCache[7:3], 1'b1, rFlagsCache[1:0]};
      end
      else begin
          rDifference[rIndex] <= ComputeDiffs(rDifference[rIndex], rDownMovement);
          rDownGradient[rIndex] <= {rDownMovement,rIndexCache,rNeighborCache,
          rDownFlags[7:3], 1'b1, rDownFlags[1:0]};
      end
    end
  end
end

 

Any suggestions will be appreciated. Again, if I comment this out of a very large design, Vivado synthesis completes in about 40 mIns. If I don't it will run over night > 15 hrs until I stop it and hangs after the Cross bondary validation point.

 

thanks

Benard

 

8 Replies
hemangd
Moderator
Moderator
1,327 Views
Registered: ‎03-16-2017

@blowe 

In any case, the tool should not hang or crash. 

Can you share this full RTL source file to reproduce the same issue at my end? So i can share with the development team to fix this issue.

If yes, I can share ezmove ftp link through which you can share the files. 

Regards,
hemangd

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blowe
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1,313 Views
Registered: ‎12-03-2019

Hemangd,

thanks for the response. The design is very large with several modules. After a month of debugging, I do know that if I comment out logic in 2 modules using the a number of 2D registers, it goes past the Cross Boundary Analysis phase. I currently a vivado synthesis running with just one of the modules which causes the full design to hang. I am hoping I can reproduce the issue with just that module. My only worry is that perhaps without the entire system design, this module will synthesize. I can send you a vivado project containing that module, perhaps you can find something obvious in the code. So let me know the ftp link to send the vivado project.

Again, any hints or ideas why this occurs will be appreciated.

thanks

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hemangd
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Registered: ‎03-16-2017

@blowe 

I have sent you ezmove ftp through which you can provide the archived project. 

We have seen such hang/crash during cross-boundary area optimization phase but to getting particular that why it is getting hang in this case, we need to investigate it after reproducing it at our end. 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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blowe
Visitor
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Registered: ‎12-03-2019

Got it. And sent the test vivado project. Hopefully that has enough information to point us in the right direction. It has been very frustrating converting into Vivado.

 

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hemangd
Moderator
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1,134 Views
Registered: ‎03-16-2017

@blowe 

I have filed CR (Change Request) with the development team to fix this issue in a future release of Vivado. 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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richardhead
Scholar
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1,115 Views
Registered: ‎08-01-2012

@hemangdcan you post what the problem is so others can avoid it?

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hemangd
Moderator
Moderator
1,093 Views
Registered: ‎03-16-2017

@richardhead , there is no wrong usage. 

Tool's behavior is incorrect due to big 2D registers.

Regards,
hemangd

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maps-mpls
Mentor
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699 Views
Registered: ‎06-20-2017

@hemangdIs this an issue on 2019.1?  Also, was it fixed by 2020.1?  I am having long synthesis due to cross boundary area optimization  even though I have -flatten_hierarchy none.  I am also using 2-d arrays and structurally connecting a small module to black box modules, and the build times are longer than I would expect, as the time it takes to synthesize in the non-project OOC synthesis is much longer than I would have guess based on the amount of logic generated.

 

 

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