01-15-2012 04:52 AM
Hi all, I am the beginner in programming in VHDL. That's my project of my FIFO memory using SPARTAN3 device RAMB16_S1_S1, but I'm sure sth is wrongly connected, because in simulation it doesn't work properly. Could you give me some help to correct these scheme?
P.S. I work only with makin connections on the page, not programming by writing a code.
01-15-2012 07:02 AM
01-16-2012 03:46 AM - edited 01-16-2012 03:50 AM
If you are drawing a schematic, then you are not designing in VHDL!
Which idiot(s) gave you this project?
I suggest that you cheat. Generate a FIFO using the tools, and use that as a template for drawing your schematic.
01-16-2012 10:51 AM
01-16-2012 11:28 AM
It looks to me like your schematic describes a "write-only" memory. I Assume at least one
of the two ports should be read-only, meaning either WEA or WEB should be connected to
ground instead of the enable signal. There may be other mistakes, but that one is a doozy!
01-16-2012 11:43 AM
01-16-2012 12:04 PM
> Thats how FIFO works.
A FIFO does not change the state of the storage element after it has been read. This does not happen until the WRITE pointer wraps around and overwrites the previous content of the storage element.