Making FIFO memory in VHDL

[jar3k]

Hi all, I am the beginner in programming in VHDL. That's my project of my FIFO memory using SPARTAN3 device RAMB16_S1_S1, but I'm sure sth is wrongly connected, because in simulation it doesn't work properly. Could you give me some help to correct these scheme?

P.S. I work only with makin connections on the page, not programming by writing a code.

[luisb]

Rather than instantiating the BRAM primitive, have you tried generating a FIFO CoreGen core? I think you'll find using a core to be easier to use.

[jar3k]

Perhaps, but in my case using BRAM is obligatory.

[rcingham]

If you are drawing a schematic, then you are not designing in VHDL!
Which idiot(s) gave you this project?
I suggest that you cheat. Generate a FIFO using the tools, and use that as a template for drawing your schematic.

[jar3k]

I'm a student and this project gave me my teacher. We are drawin the schematic and then implementing this on the board. I do not understand what you mean by saying I cheat.

[gszakacs]

It looks to me like your schematic describes a "write-only" memory.  I Assume at least one

of the two ports should be read-only, meaning either WEA or WEB should be connected to

ground instead of the enable signal.  There may be other mistakes, but that one is a doozy!

-- Gabor

[jar3k]

Hm, okay I grounded WEB and know it works (i can write and read from memory), but how to make that after reading, information is wiped out from the memory? Thats how FIFO works.

[mcgett]

> Thats how FIFO works.

A FIFO does not change the state of the storage element after it has been read.  This does not happen until the WRITE pointer wraps around and overwrites the previous content of the storage element.

[jar3k]

Ok, so it seems everything works properly. Thanks a lot!