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nicruireq
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Registered: ‎06-14-2019

Mark signals to debug in a netlist not shown

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Hi, i'm learning about in-system debugging, I'm trying this tutorial:

https://www.xilinx.com/video/hardware/logic-debug-in-vivado.html

I have a synthesized design and i want to mark as debug the otuput ports but vivado does not show "mark debug" as selectable:

foro1.png But with the signal before OBUF element i can select the "mark debug" option:

foro2.png

Why does this happen?

Thanks.

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dpaul24
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Registered: ‎08-07-2014

@nicruireq,

But with the signal before OBUF element i can select the "mark debug" option

Because the debug cannot be placed there. It connects to the FPGA pin.

For you it doesn't mak eany difference. It is just a debug point on the other side of the buffer. There is no logical change in the signal.

------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem

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dpaul24
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Registered: ‎08-07-2014

@nicruireq,

But with the signal before OBUF element i can select the "mark debug" option

Because the debug cannot be placed there. It connects to the FPGA pin.

For you it doesn't mak eany difference. It is just a debug point on the other side of the buffer. There is no logical change in the signal.

------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem

View solution in original post

hongh
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890 Views
Registered: ‎11-04-2010

Hi, @nicruireq ,

I agrees with @dpaul24 .

You can also refer to an old AR, which clarify the limitation of the signal you can observe. It can help you  understand the problem further.

https://www.xilinx.com/support/answers/38115.html

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