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Registered: ‎01-21-2016

Modify synthesized design

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Hello,

I have synthesized the design of a soft processor. It is written on Verilog.

In the Elaborated Design, the register file is created as a RTL_RAM7. This register file has an read at the same time two different registers, because it has two read ports.

 

If I look at the Synthesized design, there are two copies of the register file (composed by different RAM32M) in order to implement the two read ports.

 

My question is: could I modify the Synthesized design? It will be great to use this "redundancy" created by Vivado in the Synthesized design to create some modifications, without creating another copy of the register file in the Verilog (code) that will increase the design size.

Thank you for your help

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Guide
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Registered: ‎01-23-2009

Looking at the question directly - can you modify the Synthesized design - the answer is "Yes, but you shouldn't". There are commands within Vivado to add cells, delete cell, add nets, connect nets, etc... - these allow you to make minor changes to a netlist without have to go all the way back to RTL. In general, these are used in the later stages of the design flow, when you already have a placed and/or routed design and you need to make minor changes without redoing everything.

 

However, they are difficult to do, and they are not "permanent". If you ever do need to re-run synthesis, the changes you made will not be in the new synthesized design, and furthermore the exact Tcl commands you used to modify your design post-synthesis may not work on the new design (since the new synthesized design may have different structure, names, cells, etc...)

 

However, that being said, I don't know what you are trying to "take advantage of". Your register file has one write port and 2 read ports - the tools have correctly inferred two (simple) dual-port RAMs for this (I'm actually a bit surprised it could figure it out for itself). There is no redundancy - both ports of both RAMs are used; when a write is done to the register file, the write has to be done to both copies (to keep them consistent) - this uses the write port of each RAM. Then you have two read ports, each of which can satisfy one read operation per clock. So while two copies of the register file exist, there isn't really any redundancy - all 4 ports of the two RAMs are used.

 

Furthermore, if you changed the RTL to actually have two "redundant" register files so that your RTL has the right number of ports, it wouldn't actually change anything. You would now code for two register files, where both are updated on a register write and each one is used separately for a read. This would infer exactly the same amount of resources - two (simple) dual port RAMs.

 

Avrum

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Guide
Guide
8,232 Views
Registered: ‎01-23-2009

Looking at the question directly - can you modify the Synthesized design - the answer is "Yes, but you shouldn't". There are commands within Vivado to add cells, delete cell, add nets, connect nets, etc... - these allow you to make minor changes to a netlist without have to go all the way back to RTL. In general, these are used in the later stages of the design flow, when you already have a placed and/or routed design and you need to make minor changes without redoing everything.

 

However, they are difficult to do, and they are not "permanent". If you ever do need to re-run synthesis, the changes you made will not be in the new synthesized design, and furthermore the exact Tcl commands you used to modify your design post-synthesis may not work on the new design (since the new synthesized design may have different structure, names, cells, etc...)

 

However, that being said, I don't know what you are trying to "take advantage of". Your register file has one write port and 2 read ports - the tools have correctly inferred two (simple) dual-port RAMs for this (I'm actually a bit surprised it could figure it out for itself). There is no redundancy - both ports of both RAMs are used; when a write is done to the register file, the write has to be done to both copies (to keep them consistent) - this uses the write port of each RAM. Then you have two read ports, each of which can satisfy one read operation per clock. So while two copies of the register file exist, there isn't really any redundancy - all 4 ports of the two RAMs are used.

 

Furthermore, if you changed the RTL to actually have two "redundant" register files so that your RTL has the right number of ports, it wouldn't actually change anything. You would now code for two register files, where both are updated on a register write and each one is used separately for a read. This would infer exactly the same amount of resources - two (simple) dual port RAMs.

 

Avrum

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Registered: ‎01-21-2016

Thank you avrumw for your answer, your explanation is crystal clear.

 

I'll take your advice and search for another approach.

 

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